Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit
Reexamination Certificate
1999-08-06
2001-12-18
Neal, Regina Y. (Department: 2753)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Head amplifier circuit
C360S068000
Reexamination Certificate
active
06331919
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to write driver circuits for magnetic recording. More particularly, the present invention relates to write driver circuits for high data rate magnetic recording and techniques for fabricating such write driver circuits.
2. Description of the Related Art
FIG. 1
shows a high RPM disk drive
10
having a magnetic read/write head (or a recording slider) that is positioned over a selected track on a magnetic disk
11
for recording data using a servo system. The stage servo system includes a voice-coil motor (VCM)
13
for coarse positioning a read/write head suspension
12
and may include a microactuator, or micropositioner, for fine positioning the read/write head over the selected track.
FIG. 2
shows an enlarged exploded view of the read/write head end of suspension
12
in the case when a microactuator is also being used. An electrostatic rotary microactuator
14
is attached to a gimbal structure
15
on suspension
12
, and a slider
16
is attached to the microactuator. A read/write head
17
is fabricated as part of slider
16
.
For high data rate magnetic recording, the write path of a recording channel front-end requires a wide bandwidth and short waveform rise and fall times in order to accurately transfer high-frequency write data patterns to a magnetic medium) such as a disk. The virite signal includes abrupt switching, that is, polarity reversals of the signal, that represent the information that is to-be-recorded. The abrupt switching generates high-frequency harmonics that must be transferred from the write driver to the magnetic write transducer (write head) in order that the write signal is accurately transferred onto the magnetic medium.
Conventional write drivers have a high output impedance, essentially forming a current source for the write current needed to drive an inductive write head. The output impedance is much greater than the head input impedance.
FIG. 3
shows a conventional write driver circuit
30
that is connected directly to the (bonding) terminals of a magnetic write transducer (write head)
32
through a suspension interconnect
31
. Write driver circuit
30
is configured as a current commutating write-driver circuit and includes two switches S and two switches {overscore (S)} that are connected in an H configuration. An obstacle in transferring the write data output signal from write driver circuit
30
to write head
32
is in the propagation of the write signal along interconnect
31
between write driver circuit
30
and the write head
32
.
The invention described below improves the propagation of the write signal along an interconnect between a write driver circuit and a write head, while maintaining the signal integrity, i.e., the signal properties essential for high data rate writing.
SUMMARY OF THE INVENTION
The present invention provides a technique for improving propagation of the write signal along an interconnect between a write driver circuit and a write head. The advantages of the present invention are provided by a magnetic recording circuit that includes an electronic write driver output stage having a write signal output, a magnetic write head having a write signal input and an interconnect circuit having a selected characteristic impedance Z
0
. The input of the interconnect circuit is coupled to the write signal output of the write driver output stage, and the output of the interconnect circuit is coupled to the write signal input of the write head. According to the invention, the interconnect circuit can be one of, or both, source-terminated and load-terminated. When the interconnect circuit is source-terminated, the write driver output stage includes a source-terminating circuit so that an output impedance Z
D
formed by the write driver output stage and the source-terminating circuit is substantially equal to the selected characteristic impedance Z
0
of the interconnect circuit. When the interconnect circuit is load-terminated, the magnetic write head includes a load-terminating circuit so that an input impedance Z
l
formed by the magnetic write head and the load-terminating circuit is substantially equal to the characteristic impedance Z
0
of the interconnect circuit.
When the write driver output stage is a current-type write driver having an output impedance that is greater than the characteristic impedance Z
0
of the interconnect circuit, the source-terminating circuit is a resistance that is connected in shunt across the output impedance of the write driver output stage. Thus, the output impedance Z
D
formed by the impedance of the write driver output stage and the source-terminating circuit is substantially equal to the selected characteristic impedance Z
0
of the interconnect circuit. Alternatively, when the write driver output stage is a current-type write driver output stage having an output impedance that is greater than the selected characteristic impedance Z
0
of the interconnect circuit, the magnetic recording circuit further includes a feedback circuit connected in parallel with the current-type write driver output stage. The feedback circuit reduces the output impedance of the output stage so that the output impedance of the write driver substantially equals the selected characteristic impedance Z
0
of the interconnect circuit. When the write driver output stage is a voltage-type write driver output stage having an output impedance that is less that the characteristic impedance Z
0
of the interconnect circuit, the source-terminating circuit is a resistance connected in series with the output impedance of the write driver output stage. As such, the output impedance Z
D
formed by the impedance of the write driver output stage and the source-terminating circuit is substantially equal to the selected characteristic impedance Z
0
of the interconnect circuit.
According to the invention, the load-terminating circuit is formed by electrical components that are external to the magnetic write head, and can be mounted on a suspension of the interconnect circuit. Alternatively, the electrical components that are external to the magnetic write head can be fabricated on a slider and integrated with the magnetic write head using the same fabrication processing.
When the magnetic write head includes a coil having an inductance L
h
and a resistance R
h
, and the load terminating circuit includes a first resistance R
ex
connected in a first series circuit with the coil of the magnetic write head, and a second resistance R connected in a second series circuit with a capacitance C, the first and second series circuits are connected in parallel across the output of the interconnect circuit. The characteristic impedance Z
0
of the interconnect circuit, the inductance L
h
of the coil, the resistance R
h
of the coil, and the first resistance R
ex
, the second resistance R and the capacitance C of the load-terminating network are related by
Z
0
≃
R
≃
R
ex
+
R
h
≃
L
h
C
.
When the magnetic write head includes a coil having an inductance L
h
, a resistance R
h
, and a parasitic capacitance C
par
, and the load-terminating circuit includes a first resistance R
ex
connected in a first series circuit with the coil of the magnetic write head, and a second resistance R connected in a second series circuit with a capacitance C, the first and second series circuit are connected in parallel across the output of the interconnect circuit. The characteristic impedance Z
0
of the interconnect circuit, the inductance L
h
, the resistance R
h
and the parasitic capacitance C
par
of the coil, and the first resistance R
ex
, the second resistance R and the capacitance C of the load-terminating circuit are related by
Z
0
≃
R
≃
R
ex
+
R
h
≃
L
h
-
C
par
⁢
R
h
2
C
.
REFERENCES:
patent: 5121273 (1992-06-01), Slezak
patent: 5309298 (1994-05-01), Klaasen et al.
patent: 5440434 (1995-08-01), Kanegae
patent: 5491597 (1996-02-01), Bennin et al.
patent: 5608591 (1997-03-01), Klaass
Klaassen Klaassen Berend
Van Peppen Jacobus Cornelis Leonardus
Banner & Witcoff , Ltd.
International Business Machines - Corporation
Neal Regina Y.
Tran, Esq. Khanh Q.
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