Dynamic magnetic information storage or retrieval – General recording or reproducing – Specifics of the amplifier
Reexamination Certificate
2000-10-12
2004-01-20
Holder, Regina N. (Department: 2651)
Dynamic magnetic information storage or retrieval
General recording or reproducing
Specifics of the amplifier
C360S046000, C327S110000
Reexamination Certificate
active
06680809
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a write head current damping circuit with dynamic coupling. More particularly, the present invention relates to a write head current damping circuit which minimizes high frequency ringing in write driver circuits, thereby minimizing current overshoot during a transient response period, while maintaining maximum write current drive to the write head.
2. Description of Related Art
Generally, a write driver circuit for a tape product is used to write data onto a tape.
FIG. 1
is circuit diagram of a conventional write head/cable circuit
100
. The write head/cable load
10
consists of an inductive/capacitive (reactive) and resistive loads. To write data to tape, the write head is driven with alternating polarities of a DC current, I
s
. By flipping the polarity of the load current, I
s
, domains on a tape are set, thereby writing data to the tape. In the example of
FIG. 1
, data signal D and its compliment D_ are inputs into inverter
2
and inverter
4
, respectively. Each of inverter
2
and inverter
4
receive write voltage, V
s
, from the source
6
and output either 0 or V
s
volts alternatively, depending on whether D is high or low. Resistor, R
s
loads the head/cable
10
to deliver current, I
s
, to the head.
FIG. 2
is the equivalent of the write driver circuit
100
of
FIG. 1
, including write driver
6
, and the write head/cable
12
, where driver
6
is the source, and load
10
is composed of the write head and cable. Voltage source, V
s
, is the output voltage of write driver
6
, and V
o(s)
is the voltage across the load
10
. Z
s
is the output impedance of write driver
6
. As a general statement, the cable operates to couple the write driver
6
to the write head so that power may be supplied from V
s
to the write head. C
c
represents the capacitance of the cable. R
h
and L
h
represent the resistance and inductance respectively, i.e. reactance, of the head. For ease of explanation, where source impedance, Z
s
, is a resistor, R
s
, circuit analysis of write driver circuit of
FIG. 2
results in the following equation (equation 1) for V
o(s)
:
V
o
(
s
)
=
(
R
h
/
(
R
h
+
R
s
)
)
*
[
1
+
(
L
h
/
R
h
)
]
s
1
+
[
R
s
R
h
C
c
/
(
R
s
+
R
h
)
+
L
h
/
(
R
s
+
R
h
)
]
s
+
[
R
s
L
h
C
c
/
(
R
s
+
R
h
)
]
s
2
*
V
s
(
Eq
.
1
)
The denominator on the right side represents a second order system, wherein there is a damping factor proportional to the coefficient, [R
s
R
h
C
c
/(R
s
+R
h
)+L
h
/(R
s
+R
h
)], of the first order term. Inherently, the reactance of the coupling cable introduces high frequency ringing during transient response, thereby generating an overshoot in the transient response of load current. This is illustrated by current overshoots
20
a
and
20
b
of waveform
20
in FIG.
5
. Waveform
20
represents the alternating write driving signal to the head and generally includes a transient period and a steady state period, where data is written during the steady state period. As seen in waveform
20
, the aforementioned damping factor does little to minimize the overshoot.
In applications that require faster current rise times in response to an increase in tape speed and/or faster data writing capabilities, one solution in the art has been to reduce the inductance of the cable. However, a lower inductance causes a decrease in the damping factor, and therefore, an increase in overshoot.
Various current damping circuits for minimizing overshoot in write circuits are known. One such technique is illustrated by the equivalent write driver circuit of FIG.
3
. In this approach, a damping resistor, R
D
, is placed in parallel with the write head. The resultant modifications of source resistance, R
s
, and source voltage, V
s
(with respect to equation 1 above):
R
s
is replaced by
R
s
(
R
D
/(
R
D
+R
s
))
V
s
is replaced by
V
s
(
R
D
/(
R
D
+R
s
))
Note that R
s
and V
s
are both decreased by the introduction of R
D
. The decreased R
s
increases the term, L
h
/(R
s
+R
h
), of the damping factor, [R
s
R
h
C
c
/(R
s
+R
h
)+L
h
/(R
s
+R
h
)]. Note that R
D
does not significantly effect the term, R
s
R
h
C
c
/(R
s
+R
h
), since R
s
, which is significantly greater than R
h
, exists both in the numerator and denominator. While this increase in damping factor effectively reduces the overshoot, the damping resistor also loads the driver circuit, which reduces V
s
in equation 1 above, thereby reducing the current available to the write head. This is illustrated by the decreased DC current drive of waveform
22
of FIG.
5
. One solution to this consequence has been to increase the drive capability of the write driver to handle the added loading of the damping resistor. This solution requires that it be feasible to increase the drive capability of the write driver, which is not always the case. Further, the excess power supplied by the driver is not utilized for the write head, and is dissipated as heat.
As is apparent from the discussion above, these techniques have failed to minimize the overshoot characteristic of a write signal while preventing an unnecessary load to the write driver circuitry.
SUMMARY OF THE INVENTION
Accordingly, the present invention solves the aforementioned drawbacks of the prior art by limiting or removing the overshoot during the transient response period of a data writing signal supplied to a write head, without loading the write head during steady state (data writing) periods.
In one embodiment, the present invention provides a write head current damping circuit. The circuit includes a write head cable coupled to write head, the write head and the cable receiving a write signal. The circuit also includes a damping circuit comprising a damping element. Preferably, the damping circuit is adapted to couple the damping element to the write head during a transient period of the write signal, and also adapted to decouple the damping element from the write head during a steady state period of the write signal.
In another embodiment, the present invention provides a write head current damping circuit, comprising a write head defining a reactive load; a write head cable coupled to the write head and defining an impedance load; and a damping circuit coupled to the write head, and defining a damping load to a write signal during a transient response period of the write head and the cable, and further defining an open circuit during a steady state period of the write head and the cable.
In method form, the present invention provides a method for damping the transient response of a write head comprising the steps of: supplying a write signal to a write head; coupling a damping element to the write head during a transient period of the write signal; and decoupling said damping element from said write head during a steady state period of the write signal.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to preferred embodiments and methods of use, the present invention is not intended to be limited to these preferred embodiments and methods of use. Rather, the present invention is intended to be limited only as set forth in the accompanying claims.
REFERENCES:
patent: 4159489 (1979-06-01), Braitberg
patent: 4314288 (1982-02-01), Gyi
patent: 4722010 (1988-01-01), Suzuki et al.
patent: 5291385 (1994-03-01), Vinciarelli
patent: 5566060 (1996-10-01), Shimer et al.
patent: 5856740 (1999-01-01), Rau et al.
patent: 5880626 (1999-03-01), Dean
patent: 6128146 (2000-10-01), Ngo
patent: 6297919 (2001-10-01), Pidutti et al.
Malmberg James Ernest
Tretter Larry LeeRoy
Holder Regina N.
Pfleger Edmund P.
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