Write current driving circuit

Details Write current driving circuit Write current driving circuit

1999-07-08

2001-03-13

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S423000, C327S588000

Reexamination Certificate

active

06201421

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a write current driving circuit used for a hard disk drive (HDD), a floppy disk drive (FDD) or the like.
BACKGROUND OF THE INVENTION
FIG. 8
is a circuit diagram showing a write current driving circuit based on the conventional technology. This write current driving circuit comprises two NPN transistors T
1
, T
2
on the current-supply side; two NPN transistors T
3
, T
4
on the current-extraction side; a write head WH made up of a coil; two NPN transistors T
5
, T
6
for biasing a base potential of the transistors T
1
, T
2
; and two loading resistors R
1
, R
2
.
Collectors of the transistors T
1
and T
2
are connected to a power supply unit Vcc. Bases of the transistors T
1
and T
2
are connected to the power supply unit Vcc through the resistors R
1
and R
2
respectively. Emitters of the transistors T
1
and T
2
are connected to the collectors of the transistors T
3
and T
4
respectively.
Signals IN
1
and IN
2
inputted from external devices are supplied as base potentials to the bases of the transistors T
3
and T
4
respectively. The input signal IN
2
is an inverted signal of the other input signal IN
1
. Emitters of the transistors T
3
and T
4
are commonly connected to a current source
11
, thus a current flows from the emitters of the transistors T
3
and T
4
into the current source
11
.
Collectors of the transistors T
5
and T
6
are connected to the bases of the transistors T
1
and T
2
respectively. Base potentials are fed by the signals IN
1
and IN
2
to the bases of the transistors T
5
and T
6
respectively. Emitters of the transistors T
5
and T
6
are commonly connected to a current source
12
, thus a current flows from the emitters of the transistors T
5
and T
6
into the current source
12
.
One end of the coil of the write head WH is connected to the emitter of the transistor T
1
and the collector of the transistor T
3
. The other end is connected to the emitter of the transistor T
2
and to the collector of the transistor T
4
.
Effects of the write current driving circuit configured as shown in
FIG. 8
will be described below. When one input signal IN
1
is at a relatively high potential level (described as HIGH hereinafter) and the other input signal IN
2
is at a relatively low potential level (described as LOW hereinafter), the transistors T
3
and T
5
are ON, while the transistors T
4
and T
6
are OFF.
As the transistor T
5
is ON, a current passes through the loading resistor R
1
. With that current, a base potential of the transistor T
1
drops and the transistor T
1
is turned OFF. On the other hand, as the transistor T
6
is OFF, a current does not pass through the loading resistor R
2
. Accordingly, a base potential of the transistor T
2
is maintained at the power supply potential as it is, and so the transistor T
2
is turned ON. Therefore, an emitter current of the transistor T
2
passes through the write head WH from the side of the transistor T
2
toward the side of the transistor T
3
, and becomes a collector current of the transistor T
3
.
When the input signal IN
1
is LOW and the other input signal IN
2
is HIGH, the transistors T
3
and T
5
are OFF while the transistors T
4
and T
6
are ON. Accordingly, a current passes through the loading resistor R
2
, and with that current, a base potential of the transistor T
2
drops, and the transistor T
2
is turned OFF. On the other hand, as the transistor T
5
is OFF, a current does not pass through the loading resistor R
1
, and so a base potential of the transistor T
1
is maintained at the power supply potential as it is, and the transistor T
1
is turned ON.
Therefore, an emitter current of the transistor T
1
passes through the write head WH from the side of the transistor T
1
toward the side of the transistor T
4
, and becomes a collector current of the transistor T
4
. As described above, by inputting a pair of inverted signals IN
1
and IN
2
, a current passing through the write head WH, namely a direction of a write current to a disk is switched.
In recent years, it has been desired that data is written in a hard disk or the like with higher speed. To increase the writing speed, it is required to increase the switching speed when a direction of a write current is switched and also to speed up a rise time (Tr) and a fall time (Tf) of the current on switching.
In the conventional type of write current driving circuit shown in
FIG. 8
, however, there are base-emitter capacitor and base-collector capacitor in input sections of the transistors T
1
and T
2
, and the capacities form a low-pass filter together with the loading resistors R
1
and R
2
. The formed filter makes frequency response worse, and so the rise time and the fall time of a write current when the direction of the write current is switched becomes longer. If resistances of the loading resistors R
1
and R
2
are made smaller to overcome the problem, a current required to supply a base voltage to the transistors T
1
and T
2
becomes larger, which requires larger power consumption.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain, for the purpose of solving the problems as described above, a write current driving circuit with which switching a direction of a write current can be speeded up with suppressed power consumption.
With the present invention, the ON/OFF state of a first PMOS transistor and a first NMOS transistor switches concurrently, the ON/OFF state of the first PMOS transistor and a second PMOS transistor switches concurrently, and the ON/OFF state of a second PMOS transistor and a second NMOS transistor switches concurrently, and so a direction of a current passing through a resistive element changes in response to switching of the ON/OFF state among those PMOS transistors and NMOS transistors. Only when the first PMOS transistor, second PMOS transistor, first NMOS transistor, and second NMOS transistor switch from an OFF state to an ON state, the third PMOS transistor, fourth PMOS transistor, third NMOS transistor, and fourth NMOS transistor are turned ON.
With the present invention, ON/OFF of a first current-supply transistor is switched in response to switching of the ON/OFF state of the first PMOS transistor and first NMOS transistor, and ON/OFF of a second current-supply transistor is switched in response to switching of the ON/OFF state of the second PMOS transistor and second NMOS transistor.
With the present invention, ON/OFF of a first current-extraction transistor and a second current-extraction transistor is switched by the switching elements connected to the emitters thereof respectively.
With the present invention, ON/OFF of a first current-supply transistor and a second current-supply transistor is switched according to the outputs from a first CMOS inverter circuit and a second CMOS inverter circuit.
With the present invention, source potentials of a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor are kept at a prespecified potential which is higher than the ground potential.
Other objects and features of this invention will become understood from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 4961144 (1990-10-01), Yabe et al.
patent: 5309347 (1994-05-01), Poma et al.
patent: 5332954 (1994-07-01), Lankin
patent: 5631595 (1997-05-01), Lakshmikumar
patent: 5781026 (1998-07-01), Chow
patent: 5852526 (1998-12-01), Huntington
patent: 5892382 (1999-04-01), Ueda et al.
patent: 9-219004 (1997-08-01), None

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