Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1998-04-16
1999-10-12
Nelms, David
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
G11C 800
Patent
active
059663421
ABSTRACT:
A write control driver circuit stores a data in a high speed chip by causing an enabling timing of a write control signal to become faster. The circuit includes a first logic circuit for receiving a peri-top address transition detection signal and a peri-bottom address transition detection signal, and a second logic circuit for receiving a combined address transition detection signal, a coding signal and a write driver signal, each having a predetermined width. The combined address transition detection signal is generated based on a delay unit having a prescribed pulse width. The second logic circuit outputs a write control signal that is not controlled by the peri-top address transition detection signal and the peri-bottom address transition detection signal.
REFERENCES:
patent: 4744063 (1988-05-01), Ohtani et al.
patent: 5267216 (1993-11-01), Gabillard et al.
patent: 5307324 (1994-04-01), Nishimoto
patent: 5548560 (1996-08-01), Stephens, Jr. et al.
patent: 5740123 (1998-04-01), Uchida
patent: 5825693 (1998-10-01), Lee et al.
LG Semicon Co. Ltd.
Nelms David
Tran M.
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