Write control circuit for semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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36518901, G11C 1600

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active

06061272&

ABSTRACT:
A write control circuit that generates a control signal to initiate a write operation for a semiconductor memory device, such as an EEPROM, compensates for fluctuations in the supply voltage. The write control circuit includes a control potential generator that produces a first control potential which is kept higher than the ground potential and a second control potential which is kept lower than the supply potential. A first transistor is connected to the supply potential and receives a write potential at its gate. A second transistor is connected between the first transistor and ground and receives the first control potential at its gate. A third transistor is connected to the supply potential and receives the second control potential at its gate. A fourth transistor is connected between the third transistor and ground and receives a potential from a first node between the first and second transistors at its gate. The control signal is generated at a second node between the third and fourth transistors. The control signal is activated when the write potential reaches a certain value.

REFERENCES:
patent: 4977543 (1990-12-01), Youzi
patent: 5253201 (1993-10-01), Atsumi et al.
patent: 5388084 (1995-02-01), Itoh et al.
patent: 5801987 (1998-09-01), Dinh

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