Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-02-10
2000-06-27
Lane, Jack A.
Static information storage and retrieval
Addressing
Sync/clocking
3652335, 365194, G11C 700
Patent
active
060814756
ABSTRACT:
A memory device includes a low complexity, easy delay tuning, balanced-delay "combine control signals" (CCS) block, driven by slow slope control signals directly from the first stage (preferably not later than a weak inverter used in the hysteresis feedback portion) of a stabilized trip point input buffer. The CCS block is able to generate global internal write pulses appropriately timed with respect to circuits gating a data write to bitline access with an address transition detection (ATD) pulse, in order to provide stable, improved and balanced (between a plurality of control signals which can individually initiate and/or end a write in multiple distinct combinations) write parameter margins for the memory device. A three-step delay adjustment method for the CCS block and related data delay blocks is also provided. Additionally, intermediately generated signals in the CCS block are used for read-control, and a quarter-targeted data write bus enabling technique allows standby and transient current reduction in an improved trade-off with the chip enable access time for the memory device.
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Cypress Semiconductor Corporation
Lane Jack A.
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