Write command and write data timing circuit and methods for...

Details Write command and write data timing circuit and methods for... Write command and write data timing circuit and methods for...

2011-06-28

2011-06-28

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230060, C365S236000

Reexamination Certificate

active

07969813

ABSTRACT:
Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

REFERENCES:
patent: 6438055 (2002-08-01), Taguchi et al.
patent: 7872924 (2011-01-01), Ma
patent: 2001/0015924 (2001-08-01), Arimoto et al.
patent: 2010/0165769 (2010-07-01), Kuroki

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