Write circuit for large MRAM arrays

Details Write circuit for large MRAM arrays Write circuit for large MRAM arrays

2001-04-05

2002-03-26

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

Magnetic

C365S173000

Reexamination Certificate

active

06363000

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to random access memory for data storage. More specifically, the invention relates to a magnetic random access memory device including an array of memory cells and circuitry for writing data to the memory cells.
Magnetic Random Access Memory (“MRAM”) is a type of non-volatile memory that is being considered for long-term data storage. Accessing data from MRAM devices would be orders of magnitude faster than accessing data from conventional long-term storage devices such as hard drives. Additionally, the MRAM devices would be more compact and would consume less power than hard drives and other conventional long-term storage devices.
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
Each memory cell stores a bit of information as an orientation of a magnetization. The magnetization orientation of each memory cell can assume one of two stable orientations at any given time. These two stable orientations of magnetization, parallel and anti-parallel, represent logic values of “1” and “0.”
A write operation on a selected memory cell is performed by supplying write currents to the word and bit lines crossing the selected memory cell. The write currents induce an external magnetic field that sets the orientation of magnetization in the selected memory cell. The magnetization orientation is determined by the direction of the external magnetic field. The direction of the external magnetic field, in turn, is determined by the direction of the write currents flowing through the word and bit lines.
Data is typically written to the MRAM array as n-bit words. For instance, a 16-bit word might be written to sixteen memory cells by supplying a write current to a word line crossing the sixteen memory cells and supplying separate write currents to the sixteen bit lines crossing the sixteen memory cells.
There are a number of challenges to designing a write circuit for a large MRAM array. One challenge is reducing peak write currents without degrading the write performance of the MRAM array. High peak currents can overstress parts of the write circuit and generate unacceptable levels of current noise. Moreover, high peak currents can damage the memory cells.
Another challenge is controlling the write currents to a specified range. The write currents should be controlled to a specified range in order to perform reliable write operations. Too small a write current might not cause a selected memory cell to change its orientation of magnetization, and too large a write current will disturb unselected memory cells.
This challenge is complicated by the need for a write current that is bi-directional. Typically, bit line current flows in one direction to set a parallel magnetization orientation, and it flows in an opposite direction to set an anti-parallel magnetization orientation.
This challenge is further complicated by resistive cross-coupling between the memory cells. Each memory cell may be represented as a resistive element, and the stored data may be represented by a small differential resistance. In an MRAM array, each resistive element is coupled to other resistive elements. The write currents can be affected by resistive cross-coupling of the selected memory cell with unselected memory cells.
SUMMARY OF THE INVENTION
These design challenges are met by the present invention. According to one aspect of the present invention, an MRAM device includes a write circuit that writes a data word to a plurality of memory cells by supplying a write current to a word line crossing the memory cells, and supplying current pulses to bit lines crossing the memory cells. At least some current pulses are supplied to the bit lines in a staggered sequence. Consequently, peak write current is reduced.
According to another aspect, a write circuit applies write currents to selected word and bit lines and connects both ends of each unselected line to a high impedance. Consequently, effects of resistive cross-coupling, such as parasitic currents, are reduced and the write currents are controlled to a specified range.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 3984815 (1976-10-01), Drexier et al.
patent: 4805146 (1989-02-01), Bruder et al.
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 5793697 (1998-08-01), Sheuerlein
patent: 6055178 (2000-04-01), Naji

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