Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1993-03-30
1994-03-29
Wambach, Margaret R.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
3072961, 3072963, 365227, 365229, H03K 17687, H03K 301
Patent
active
052988163
ABSTRACT:
A write assist circuit for CMOS inverter-type memory cells and latches having means for choking current flow from a voltage level source to power supply terminals of a group of such memory cells or latches during a data loading or write cycle. The write assist circuit has a pair of pass transistors that respectively connect to one or two voltage level sources. In one embodiment, both pass transistors connect in parallel to a single voltage level source, one transistor always active being of low conductance, the other transistor of normal conductance being turned off by a write enable signal. In another embodiment, both pass transistors are of normal conductance but are respectively enabled and disabled by a write enable signal and are connected to different voltage level sources so as to supply a lower power supply voltage to the CMOS inverter-type memory cells or latches during a write cycle.
REFERENCES:
patent: 4876669 (1989-10-01), Yamamoto et al.
patent: 4910711 (1990-03-01), Guo
patent: 4953127 (1990-08-01), Nagahashi et al.
patent: 5010521 (1991-04-01), Matsui
patent: 5046052 (1991-09-01), Miyaji et al.
patent: 5226014 (1993-07-01), McManus
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