Write buffer for a digital processing system

Details Write buffer for a digital processing system Write buffer for a digital processing system

1989-09-14

1990-09-25

Heckler, Thomas M.

Boots, shoes, and leggings

3642391, 3642397, 36424612, G06F 1200

Patent

active

049597710

ABSTRACT:
The invention comprises a write buffer system which provides residence time information that increases the merge potential and enhances the write collapse feature of a "smart" buffer. The write buffer has multiple buffer locations for storing data received from a central processor, a data merger for merging data designated by the central processor for subsequent storage in contiguous memory locations, and a write controller for selectively writing the data from the plurality of write buffer locations to the memory. The system further includes time stamp registers in communication with the write controller for storing and updating a time signal representative of the write buffer location having most recently received data. The controller is responsive in part to the time signal, and inhibits the writing to memory of the data in the write buffer location having most recently received data since this is the location most likely to be eligible for a data merge. This feature decreases the number of interruptions to the CPU for data transfer operations.

REFERENCES:
patent: 4433394 (1984-02-01), Torii et al.
patent: 4507731 (1985-03-01), Morrison
patent: 4542457 (1985-09-01), Mortensen et al.

Affiliated with

Also associated with

Rating

Write buffer for a digital processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Write buffer for a digital processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write buffer for a digital processing system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-332610