Boots – shoes – and leggings
Patent
1994-04-15
1996-09-10
Shah, Alpesh M.
Boots, shoes, and leggings
395420, 364240, 36424231, 3642434, 3642456, 3642601, 364DIG1, G06F 1200
Patent
active
055553982
ABSTRACT:
A system and method for guaranteeing coherency between a write back cache and main memory in a computer system that does not have the bus level signals for a conventional write back cache memory. Cache coherency can be maintained by writing back all modified data in the cache prior to execution of the command that initiate the DMA or Bus Master transfer to or from main memory. When bus snooping logic detects writes from the CPU, the cache and main memory are synchronized. After synchronization, the bus snooper continues to look for access hits to modified data in the cache. If hits occurs and it is a DMA cycle, the CPU is prevented from further accesses to cache until after the DMA transfer, modified bytes are written back to main memory. If it is a bus master device seeking access to main memory, the CPU is prevented from further accesses to cache until the modified bytes are written back to main memory.
REFERENCES:
patent: 4167782 (1979-09-01), Joyce et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5247648 (1993-09-01), Watkins et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5353423 (1994-10-01), Hamid et al.
Intel Corporation
Shah Alpesh M.
LandOfFree
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