Write-assist and power-down circuit for low power SRAM...

Details Write-assist and power-down circuit for low power SRAM... Write-assist and power-down circuit for low power SRAM...

2009-08-25

2010-11-16

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Powering

C365S154000

Reexamination Certificate

active

07835217

ABSTRACT:
Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

REFERENCES:
patent: 5301147 (1994-04-01), Guo et al.
patent: 5581500 (1996-12-01), D'Souza
patent: 5898610 (1999-04-01), Greason
patent: 7400545 (2008-07-01), Ramaraju et al.
patent: 7466581 (2008-12-01), Huang et al.
patent: 7486586 (2009-02-01), Fifield et al.
patent: 7596012 (2009-09-01), Su et al.
patent: 2006/0268647 (2006-11-01), Yamaoka et al.
patent: 2007/0236983 (2007-10-01), Wang et al.
patent: 2008/0055967 (2008-03-01), Houston et al.

Affiliated with

Also associated with

Rating

Write-assist and power-down circuit for low power SRAM... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Write-assist and power-down circuit for low power SRAM..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write-assist and power-down circuit for low power SRAM... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4172966