Write address synchronization useful for a DDR prefetch SDRAM

Details Write address synchronization useful for a DDR prefetch SDRAM Write address synchronization useful for a DDR prefetch SDRAM

2006-05-30

2006-05-30

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S240000

Reexamination Certificate

active

07054222

ABSTRACT:
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.

REFERENCES:
patent: 5062080 (1991-10-01), Goldsmith
patent: 5384750 (1995-01-01), Lee
patent: 6067632 (2000-05-01), Yamaguchi
patent: 6636446 (2003-10-01), Lee et al.

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