Wrap-resistant ultra-thin integrated circuit package fabrication

Details Wrap-resistant ultra-thin integrated circuit package fabrication Wrap-resistant ultra-thin integrated circuit package fabrication

1996-05-10

1999-01-26

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With semiconductor element forming part

257696, 257713, 257790, 257796, H01L 2331, H01L 2336

Patent

active

058641750

ABSTRACT:
The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

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Information allegedly written by Emory Garth regarding "Memory Stacks," Applicant received a facsimile from Emory Garth on Jan. 26, 1993, Applicant does not know when this information was written or its validity.
Catalog of Dense-Pac Microsystems, Inc. describing two products: DPS512X16A3 Ceramic 512K .times.16 CMOS SRAM Module and DPS512X16AA3 High Speed Ceramic 512K .times.16 CMOS SRAM Module, pp. 865-870.

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