Wrap-around logic for interprocessor communications

Details Wrap-around logic for interprocessor communications Wrap-around logic for interprocessor communications

1985-12-06

1987-01-27

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1516

Patent

active

046398600

ABSTRACT:
A minicomputer system is disclosed having a bus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling an alternate route for issuing instructions from one processor to another. The logic detects information that is not to be transferred to the I/O devices and accordingly reroutes it back to the central processor and/or subprocessors.

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patent: 4281380 (1981-07-01), DeMesa, III et al.
patent: 4379340 (1983-04-01), Holtey et al.
patent: 4494190 (1985-01-01), Peters

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