Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-05-08
2002-04-16
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S118000, C438S125000, C438S612000, C257S700000
Reexamination Certificate
active
06372543
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates, in general, to the field of integrated circuit packages and, more particularly, to a wrap-around interconnected design for conventional ball grid array based integrated circuit manufacturing.
BACKGROUND OF THE INVENTION
During the manufacture and assembly of integrated circuits, the packaging process is one of the most critical steps. In fact, the cost of packaging an integrated circuit package can easily exceed the cost of manufacturing the integrated circuit chip. The increase in cost is due to the fact that the majority of device failures are generally packaging oriented. Therefore, there is a need for improved methods for packaging integrated circuits that reduce the cost of manufacturing and increase the reliability of the device.
A key step in integrated circuit fabrication is packaging the silicon chip in a manner that protects it in subsequent manufacturing steps and from the environment of its intended application. A critical step in the packaging process involves the inter-connection between the integrated circuit silicon chip and the board or substrate to which it is connected.
The packaging of an integrated circuit generally involves attaching an individual chip to a lead frame where, following wire bond and encapsulation, designated parts of the lead frame become the terminals of the package. Additionally, due to the increased miniaturization of integrated circuits, there has been a need to reduce both the size of the inter-connects between the silicon chip and the substrate, and also of the routing lines on the substrate. Concomitantly with the routing lines, the creation of vias within the substrate requires increased miniaturization.
U.S. Pat. No. 5,561,594 (SGS-Thomson Microelectronics, Ltd.) discloses an electrical assembly in which the electrical component is mounted on a multi-layer printed circuit board having a plurality of conducting pins located in perforations within the board. The conducting pins located in the board have pointed ends that project above the board and make electric contact with solder bumps on the electrical component. While this specification describes an apparatus and method for flip-chip packaging, it does not address the need for smaller vias for use with high performance semiconductor products. Furthermore, it uses conventional methods to create a printed circuit board. As with conventional manufacturing, the printed circuit board has standard size vias that are drilled through for each individual substrate increasing processing time.
U.S. Pat. No. 5,621,193 (Northrop Grumman Corp.) discloses a method for electrically connecting surface conductors to edge conductors by use of an intersecting side non-conductor substrate having a through hole in the substrate and metalization of the through hole. The electrical connections between the surface and the side include forming an intersecting ceiling plug in the via prior to cutting the intersecting side. The wraparound conduits as described, however, are vulnerable to damage during subsequent handling of the semiconductor. Furthermore, the specification does not address the need to improve integrated circuit packaging.
Thus, it has been recognized herein that a need has arisen for a simple, effective apparatus and method for providing a substrate for interconnecting integrated circuits using fine pitch ball grid array (BGA) technology. The need has also arisen for a more versatile package for medium to high performance semi-conductors, and for substrates and methods of manufacturing substrates with increased efficiency and decreased cost. Furthermore, a need has arisen for a substrate that can be made using present equipment and using standard manufacturing techniques, but which decreases the number of drilling and cutting steps involved in the formation of via interconnects in substrates.
SUMMARY OF THE INVENTION
The present invention can provide a simple, effective apparatus and method for interconnecting medium to high performance semiconductors to substrates using a fine pitch ball grid array (BGA). The present invention can increase the efficiency of the production in the manufacture of substrates for use with fine pitch BGA assemblies. The present invention can also decrease the processing time and materials needed during the manufacture of the substrate for fine pitch BGA assembly.
More particularly, the present invention is directed to an integrated circuit substrate having first and second surfaces and an edge comprising one or more semicircular vias at a substrate edge. The one or more semicircular vias extend between the first and the second surfaces of the substrate and are used to electrically connect routing strips or conduits on the first and second surfaces of the substrate. The semicircular vias are created by separating the one or more vias at the substrate edge.
In one embodiment of the present invention, the substrate is further defined as comprising routing strips integral to the substrate that connect to the one or more semicircular vias on the first and second surfaces of the substrate. The substrate can be a high temperature epoxy that may be mixed with glass fibers. The high temperature epoxy substrate can be made of, e.g., a bismalimide triazine or an FR-4 resin.
The integrated circuit package for use with the present invention may further comprise a silicon chip attached to the first surface of the substrate, the silicon chip having one or more bonding pads. Wire bonding electrically connects the bonding pads on the silicon chip with routing strips on the first surface of the substrate. The second side of the substrate may also comprises a ball grid array electrically connected to one or more of the semicircular vias.
An alternative embodiment of the present invention is an integrated circuit substrate strip comprising two or more substrate units, each unit having at least one edge, wherein the edge of the two or more units is at least partially defined by one or more conductive vias located on the common edge of the two or more units. The semicircular vias are formed by separating or cutting the one or more vias at the common edge of the units.
The present invention also includes a method for creating an integrated circuit substrate comprising obtaining a board having at least two integrated circuit substrate unit portions, drilling at least one via hole between the substrate unit portions and separating the unit portions of the board at the at least one via to separate the two integrated circuit substrate unit portions. After separation each unit portion has a semicircular via that connects the surfaces of the substrate. In another embodiment of the present method the via is made electrically conductive prior to separating the unit portions.
REFERENCES:
patent: 4288841 (1981-09-01), Gogal
patent: 4420652 (1983-12-01), Ikeno
patent: 4939792 (1990-07-01), Urbish et al.
patent: 5635670 (1997-06-01), Kubota et al.
patent: 5725640 (1998-03-01), Joshi et al.
patent: 5729896 (1998-03-01), Dalal et al.
patent: 5931685 (1999-08-01), Hembree et al.
patent: 6015722 (2000-01-01), Banks et al.
patent: 6121678 (2000-09-01), Chiu et al.
Chiu Anthony
Hundt Michael J.
Lao Tom Quoc
Siegel Harry Michael
Collins D. M.
Jorgenson Lisa K.
Picardat Kevin M.
STMicroelectronics Inc.
Venglarik Daniel E.
LandOfFree
Wrap-around interconnect for fine pitch ball grid array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wrap-around interconnect for fine pitch ball grid array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wrap-around interconnect for fine pitch ball grid array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2885289