Wordline voltage generating circuit including a voltage...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185230, C365S185030, C365S189090

Reexamination Certificate

active

11177842

ABSTRACT:
Disclosed is a voltage dividing circuit reducing effects of a parasitic capacitance and a wordline voltage generating circuit including that. The voltage dividing circuit according to an aspect of the present invention includes a first resistor, a plurality of second resistors, and a selection means. The first resistor is connected between an output voltage node and a dividing voltage node. The plurality of second resistors are connectable between the dividing voltage node and a ground. The second resistors are sequentially selected in response to a step control signal and connected to ground. In order to reduce the sum of a parasitic capacitance existing in the second resistors, the resistors are arranged in groups, and the selection means connects only that group that contains a selected resistor to the dividing voltage node.

REFERENCES:
patent: 6642768 (2003-11-01), Schell et al.
patent: 6937180 (2005-08-01), Muratov et al.
patent: 7038949 (2006-05-01), Chae et al.
patent: 7110292 (2006-09-01), Hahn et al.
patent: 7158418 (2007-01-01), Chae et al.
patent: 59-198595 (1984-11-01), None
patent: 08-096591 (1996-04-01), None
patent: 0172411 (1998-10-01), None
patent: 0657890 (1995-06-01), None
English language abstract of the Korean Publication No. 0172411.
English language abstract of the Japanese Publication No. 08-096591.
English language abstract of the Japanese Publication No. 59-198595.

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