Wordline driving circuit in semiconductor memory

Details Wordline driving circuit in semiconductor memory Wordline driving circuit in semiconductor memory

1998-10-05

2000-04-11

Phan, Trong

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365206, G11C 800

Patent

active

060495030

ABSTRACT:
The wordline driving circuit includes a noise prevention circuit in each control circuit of a subwordline drive selector. When a row signal from a sub-row decoder indicates that the associated control circuits are not to drive wordlines associated therewith, the noise prevention circuit in each control circuit is triggered to remove noise from the wordline.

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Nakamura et al, "A 29ns 64Mb DRAM with Hierarchical Array Architcture", pp. 1-6, 9 & 11.
Noda et al, "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 112-113.
Sugibayashi et al, ISSCC 93/Session3
on-volatile dynamic and experimental memories/paper Wp3.5, 1993 IEEE International Solid-State Circuits Conference, pp. 50-51.

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