Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
1999-12-30
2001-05-08
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S185100, C365S185010
Reexamination Certificate
active
06229755
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wordline driving apparatus in semiconductor memory devices, and more particularly to a wordline driving apparatus capable of preventing a delay of signal at an output line by using an output line of a single metal wiring structure and improving a transfer efficiency of a high voltage for driving a sub-wordline by using a sub-wordline driver of a CMOS distributed configuration.
2. Description of the Conventional Art
FIG. 1
shows a partial circuit diagram of a wordline driving apparatus according to a conventional art. The circuit comprises a decoding unit
100
for decoding address signals applied thereto and a sub-wordline driving unit
200
for controlling enabling of a sub-wordline in response to output signal from the decoding unit
100
.
The decoding unit
100
includes a first PMOS transistor MP
1
connected between a power supply voltage Vcc applying terminal and a node N
1
and having its gate terminal to which a precharge control signal /xp is applied; a plurality of NMOS transistors MN
1
~MN
3
connected in series between the node N
1
and a ground terminal and having their respective gate terminals to which row address signals ax
23
, ax
45
and, ax
67
are applied respectively; a first inverter (I
1
) for inverting the voltage level at the node N
1
and outputting it as a pull-up control signal pu; a second PMOS transistor MP
2
having its gate terminal to which the output signal of the first inverter I
1
is applied in a feedback manner and being interconnected in parallel with the first PMOS transistor MP
1
between the power supply voltage Vcc applying terminal and the node N
1
; and a second inverter I
2
for inverting the output signal of the first inverter I
1
and outputting it as a pull-down control signal pd.
Also, the sub-wordline driving unit
200
includes a NMOS transistor MN
5
, which functions as a pull-up driver, connected between a boosting signal pxi applying terminal and a sub-wordline SWL and having its gate terminal to which the pull-up control signal pu is applied via a NMOS transistor MN
4
having its gate terminal to which a power supply voltage Vcc is applied, and a NMOS transistor MN
6
, which functions as a pull-down driver, connected between the sub-wordline SWL and a ground terminal and having its gate terminal to which the pull-down control signal pd is applied.
Now, an operation of the wordline driving apparatus in accordance with the conventional art configured as described above will be explained briefly.
First, upon receiving a low level precharge signal /xdp, the first PMOS transistor MP
1
is turned-on and the voltage level at the node N
1
is transitted to a high level which is equal to the level of the power supply voltage Vcc.
Then, the high level signal at the node N
1
is inverted by the first inverter I
1
which in turn outputs a low level pull-up control signal pu for operating the sub-wordline driving unit
200
.
Also, a high level pull-down control signal pd is outputted through the second inverter I
2
.
Meanwhile, the output signal of the inverter I
1
, that is, the pull-up control signal pu is applied to the gate of the second PMOS transistor MP
2
which in turn turns-off, thereby allowing the voltage level at the node N
1
to be rapidly precharged to a high level when precharging.
Thereafter, the pull-up control signal pu and pull-down control signal pd are inputted to the sub-wordline driving unit
200
. More specifically, the pull-up control signal pu is inputted through the fourth NMOS transistor MN
4
, which was turned-on by the power supply voltage Vcc, to the gate of the fifth NMOS transistor MN
5
, and the pull-down control signal pd is inputted to the gate of the sixth NMOS transistor MN
6
. As a result, the fifth NMOS transistor MN
5
is turned-off and the sixth NMOS transistor MN
6
is turned-on, thereby allowing the sub-wordline connected to the gate of the pass transistor to have a low voltage level which is equal to the ground voltage level Vss.
Thereafter, if externally applied address signals ax
23
, ax
45
and, ax
67
are inputted through address pins on a chip, the voltage level at the node N
1
is transitted to a low level.
That is, high level address signals ax
23
, ax
45
and, ax
67
for selecting the corresponded cell are applied and thus the first to third NMOS transistors coupled in series are turned-on so that the voltage level at the node N
1
is transitted from a high level to a low level.
Meanwhile, since the precharge signal /xdp is disabled from a low level to a high level after initially precharging, at this time, the first PMOS transistor MP
1
is in a turn-off state.
Thereafter, the voltage level at the node N
1
is inverted by the first inverter I
1
, thereby allowing the pull-up control signal pu to be changed to a high level and the pull-down control signal pd to be changed to a low level.
Meanwhile, since the high level pull-up control signal pu is inputted to the gate of the second PMOS transistor MP
2
, the second PMOS transistor MP
2
is turned-off and thus a power supply voltage Vcc is not supplied to the node N
1
any longer.
Then, the pull-up control signal pu and pull-down control signal pd, which are output signals of the decoding unit
100
, are inputted to the sub-wordline driving unit
200
thereby allowing the fifth NMOS transistor MN
5
to be turned-on and the sixth NMOS transistor MN
6
to be turned-off. Accordingly, a high voltage of a boosting signal level is outputted to the sub-wordline.
As a result, data stored in the cell corresponding to a designated address are outputted through the turned-on pass transistor and then via bit lines BL, /BL and data bus lines DB, /DB to the outside during a read operation, and are stored on a data storage node through the pass transistor during a writing operation.
As mentioned above, when driving a word line, disadvantages of a conventional art are as follows.
First, there may greatly occur a delay of signal in the output line since the decoding unit output line made of a metal wire is consisted of two (pu signal output terminal and pd signal output terminal) so that the interval between the metal wires becomes limited and thus the width thereof becomes narrow.
Second, due to a voltage drop occurred by using the NMOS transistor MN
5
as a pull-up driver of the sub-wordline driving unit
200
, the sub-wordline driving high voltage pxi cannot sufficiently be transferred to, when enabling, the sub-wordline.
That is, since there occurs a voltage drop as much as a threshold voltage Vt of the fifth NMOS transistor MN
5
with respect to the sub-wordline driving high voltage pxi applied to the drain terminal thereof, the sub-wordline is on only a voltage level of the driving high voltage pxi minus the threshold voltage Vt, and thus the wordline is driven by the voltage level.
Consequently, it causes a turned-off width of the pass transistor to be narrow, resulting in insufficient restore of data in memory devices requiring a cell refresh such as a DRAM.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in view of the above problems and it is an object of the present invention is to provide a wordline driving apparatus capable of preventing a delay of signal of a main wordline output signal by using a single metal wiring and improving the transfer efficiency of a sub-wordline driving high voltage by using a CMOS type transistor.
In order to achieve the above objects, a wordline driving apparatus according to the preferred embodiment of the present invention comprises a decoding unit arranged on one side end of a semiconductor memory cell array, for decoding a plurality of externally inputted address signals in order to generate a main wordline output signal, with the main wordline output signal being outputted through a single metal wireing; and a sub-wordline driving unit arranged on each of the cells in a CMOS distributed configuration, for controlling a plurality of sub-wordlines in accordance with the main wordline output
Fears Terrell W.
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
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