Wordline driver circuit using ring-shaped devices

Details Wordline driver circuit using ring-shaped devices Wordline driver circuit using ring-shaped devices

1998-08-25

2001-05-22

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06236258

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits and more specifically to the layout of semiconductor devices within a semiconductor memory.
BACKGROUND OF THE INVENTION
Two considerations weigh very heavily in the design of semiconductor integrated circuits: operational performance and conservation of area within the integrated circuit (IC) or ‘chip’. Many circuit designs that provide outstanding performance must be rejected because of an ‘area penalty’, i.e. an increase in the layout area on the IC which is required to implement the circuit design. Conversely, circuit designs which offer substantial reductions in IC area are often rejected because of inadequate operating performance. Many of the patented advances in IC circuit design are those in which new paradigms and approaches are introduced in order to satisfy these seemingly conflicting objectives of performance and conservation of area.
Maximization of performance and conservation of IC area weigh very heavily in the design and layout of circuitry for memory ICs, especially dynamic random access memories (DRAMs). Among such circuitry are the wordline driver circuits for a memory. The primary function of a wordline driver circuit is to activate selected memory cells by raising or lowering the voltage on a wordline. A wordline is a conductor which is required to have long length to extend across all or a substantial part of a memory array to provide access to as many as multiple thousands of memory cells. Both the long length of the wordline and its use as the gate conductor for a great number of memory cells result in the wordline having high capacitance. Consequently, the wordline driver circuit must provide large current in order to drive the wordline between signal levels. In each new generation of DRAMs, continued expected increases in the scale of integration will require wordline conductors to extend to proportionally even greater lengths than before and to serve greater numbers of memory cells. Consequently, the increased wordline capacitance will require wordline driver circuits to have even greater device efficiency.
The ever-increasing scale of integration of ICs, especially DRAMs, requires that memory arrays be configured with vast numbers of wordlines, typically multiple thousands of wordlines per array. In addition, the available array of the IC is desirably configured in multiple banking units, each banking unit including a separate memory array, to more efficiently utilize the IC area. A wordline driver circuit must be provided for each of the multiple thousands of wordlines of a memory array. Hence, the area required by the wordline driver circuit can be a critical limitation to the utilization of the IC area. Accordingly, a layout for a wordline driver circuit is needed which provides superior operating performance while occupying less IC area than existing layouts.
To illustrate the background of the present invention,
FIG. 1
is a diagram showing the layout of a simple wordline driver which is constructed of an insulated gate field effect transistor (IGFET)
10
. With reference to
FIG. 1
, IGFET
10
includes an active area (AA
1
) in the semiconductor substrate and a gate conductor
14
which traverses the active area AA
1
in the y-direction. On respective sides of the gate conductor
14
are a source (S) and a drain (D).
In order to provide desirably high current throughput through the wordline driver, the width to length ratio (W/L) of IGFET
10
should be high. As is apparent from
FIG. 1
, the width
12
of the IGFET
10
is the extent of the gate conductor
14
over the active area AA
1
in the y-direction (from top to bottom of FIG.
1
). The width of the gate conductor
14
determines the effective length (L
eff
) of IGFET
10
. Thus, increasing the W/L ratio and the current throughput of the transistor can only be accomplished by decreasing the width of the gate conductor
14
(to decrease L
eff
of the IGFET
10
) or by increasing the active area AA
1
of the semiconductor substrate over which the gate conductor
14
extends in the y-direction. As apparent from
FIG. 1
, the linear layout of IGFET
10
requires an active area AA
1
which is relatively long in the y-direction. More efficient utilization of area is needed.
FIG. 2
shows the layout for an IGFET
20
of a “two-fingered” type of wordline driver circuit. In this two-fingered layout, the gate conductor
26
extends, like prongs
22
,
24
of a fork, in parallel conductors over the active area AA
2
. The prongs
22
,
24
of the gate conductor
26
operate as a linear gate conductor which has been bent at the middle to traverse the same active area AA at two places. The source regions (S) of the transistor lie to the outside of the prongs
22
,
24
, while the drain region (D) lies between the prongs
22
,
24
. In the layout shown in
FIG. 2
, the extent of the active area AA
2
in the y-direction is decreased relative to that of active area AA
1
shown in FIG.
1
. However, the extent of the active area AA
2
in the x-direction is increased relative to that of AA
1
(
FIG. 1
) to accommodate the parallel conductors and parallel source/drain/source arrangement of transistor elements. A still more area-conserving layout for a wordline driver is needed.
FIG. 3
shows a physical contour map for the gate conductors in a wordline driver circuit section of a DRAM IC which precedes the invention, but is not admitted to be prior art.
FIG. 3
shows yet another possible design in which a gate conductor
32
of a wordline driver circuit is single-stranded. Each gate conductor
32
is “wiggled”, i.e. shifted to one side or another on the substrate surface, in order to conserve IC area while enlarging source and drain contact areas
34
,
36
to accommodate the formation of contact studs. The layout shown in
FIG. 3
requires an active semiconductor area AA
3
which extends less in the x-direction than the layouts shown in
FIGS. 1 and 2
, but still requires the active area AA
3
to be long in the y-direction to accommodate long gate conductors
32
.
One disadvantage associated with the layout shown in
FIG. 3
is that conductors on the first wiring level (M
0
) of the IC above the gate conductors must be laid out in a pattern specifically designed to accommodate the “wiggled”, i.e. shifting gate conductor patterns therein. Another disadvantage is that the wiggled layout shown in
FIG. 3
results in a reduced number of contact points through which current can be supplied or output through source and drain terminals of each wordline driver circuit.
One problem which occurs in the design and layout of wordline driver circuits for each successive generation of DRAM is the nonscalability of channel lengths in p-type IGFET devices (PFETs). For example, with reference to
FIG. 1
, for a DRAM generation being scaled by 30% from a groundrule of 0.25 um in a first generation (a) to a groundrule of 0.175 um in generation (b), the device length L
eff
of the PFET, which is 0.45 um in generation (a), can only be scaled by 22% to 0.35 um in the later generation (b). In future generations, the PFET device length may be even less scalable than in this example.
The PFET device length L
eff
extends in the x-direction which is the direction in which adjacent wordlines of the array are spaced at critical intervals. In prior DRAM generations, a wordline driver layout such as that shown in
FIG. 2
, the required PFET device length has accommodated a “stagger-4” layout of wordline driver circuits and permitted 1 of 4 decoding. In a stagger-4 layout, groups of four wordline driver circuits are patterned parallel to each other within a given unit of active area extending in the x-direction. In the stagger-4 arrangement, the first group of four wordline driver circuits are “stacked” with a second group of four circuits which are placed adjacent to the first group but at a different location in the y-direction further away from the memory array.
It is desirable to maintain a stagger-4 layout and 1 of 4 decoding because such

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