Wordline decoder for flash memory

Details Wordline decoder for flash memory Wordline decoder for flash memory

2001-02-16

2003-03-18

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189110, C365S185270

Reexamination Certificate

active

06535430

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memory wordline decoders and more particularly to wordline decoders for flash memory.
2. Description of Related Art
Memory cells in a conventional cross-point memory array are arranged such that the control gates of cells on the same row share a common word line in the x-direction and the drain of cells on a same column share a common bit line in the y-direction. A single word can be accessed by a unique word line address and unique bit decode address. Depending upon the application, design of the word line decoder circuit and layout may be a challenging task. In SRAM applications, the voltage applied to the word line is usually VDD, the positive power supply voltage. SRAM's are optimized for fast access, so the decoding circuits are often dynamic and sized for speed. Although fast word line access is not as critical for DRAM, an additional boosted word line capability must be included within a very small memory cell pitch. In some flash memory applications, negative word line voltage decoding may be required in addition to fast access and high voltage word line decoding.
In U.S. Pat. No. 5,889,724 (Khang et al.) a wordline driving circuit is directed toward a hierarchial scheme to reduce wordline loading. U.S. Pat. No. 5,818,790 (Kim et al.) is directed toward a method for driving wordlines in a semiconductor memory device where a main row decoder generates a wordline enable signal in response to part of an address signal and a sub row decoder generates a wordline boosting signal from another part of the address signal. U.S. Pat. No. 5,602,797 (Kang) relates to improved wordline driving circuit for a memory capable of decoding a free-decoded low address to an externally applied voltage level and driving a wordline using a memory power up voltage level.
FIG. 1
shows a diagram of a prior art word line decoder for a semiconductor memory. Each word line WL is decoded
10
by a set of pre-decoded signals, and a level shifter
11
then “shifts” the logic signal voltage to its proper word line voltage. However, unless there are a sufficient number of wiring levels, the layout of the circuit of
FIG. 1
may be difficult to fit within a small memory cell pitch.
Layout is simplified for the circuit shown in
FIG. 2
, because the main decoder
21
is shared by several drivers
22
. The driver is a CMOS inverter with a decoded power supply Vdp. In addition to the inverter, there maybe a pull down NMOS device MN
5
between the wordline and ground. The gate of MN
5
is opposite in polarity to the decoded power supply. The function of the pull down device is to prevent the word line WL
0
(representing all wordlines) from floating when both the PMOS and NMOS devices are off. Although the layout for the circuit in
FIG. 2
is smaller and easier than
FIG. 1
, it does not allow for high voltage or negative voltage decoding.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a wordline decoder for high density flash memory. It is further an objective of the present invention to provide negative wordline voltage to accommodate flash memory operations. It is also an objective of the present memory to provide a wordline decoder for fast read access.
In flash memory, unlike a DRAM and SRAM, negative voltages may be required during read and erase operations. During read or verification operations, because memory cell thresholds can be less than zero, it may be desirable to apply a negative bias voltage to the selected word lines. This negative voltage may be about −1 V or −2 V, depending on the array threshold distribution characteristics. Also, applying a negative voltage to the word gate during erase has been demonstrated as an effective way to reduce the maximum voltage requirement for F-N tunneling. A negative voltage of about −4 V to −8 V may be applied to a several word lines simultaneously for block erase.
A positive high voltage may be needed during pro gram, in order to inject electrons into the floating gate. This voltage may be between 5 V to 20 V, depending on the device type and the mechanism for injection. Thus the word line decoder must be able to supply high positive voltages as well as negative voltages.


REFERENCES:
patent: 5602797 (1997-02-01), Kang
patent: 5818790 (1998-10-01), Kim et al.
patent: 5870348 (1999-02-01), Tomishima et al.
patent: 5889724 (1999-03-01), Khang et al.
patent: 5966331 (1999-10-01), Shiau et al.
patent: 6044020 (2000-03-01), Chung et al.
patent: 6166957 (2000-12-01), Chung et al.
patent: 6242962 (2001-06-01), Nakamura

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