Wordline decoder and memory device

Details Wordline decoder and memory device Wordline decoder and memory device

2006-03-21

2006-03-21

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185240

Reexamination Certificate

active

07016233

ABSTRACT:
A wordline decoder for a memory device drives a word line of a memory array and comprises a first circuit, a second circuit, and a buffer circuit. The first circuit receives voltage from a first voltage source. The second circuit receives voltage from a second voltage source. During an erase cycle, the buffer circuit receives a third voltage higher than the second voltage and lower than the first voltage. During read and program cycles, the buffer circuit receives a fourth voltage substantially equal to the first and second voltage.

REFERENCES:
patent: 4858194 (1989-08-01), Terada et al.
patent: 5566109 (1996-10-01), Matsubara
patent: 6151254 (2000-11-01), Kanamori
patent: 6754131 (2004-06-01), Kirsch et al.

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