Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-03-18
2004-03-30
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185230, C365S230080, C365S230060
Reexamination Certificate
active
06714450
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to an electrically erasable and programmable and memory (EEPROM).
BACKGROUND OF THE INVENTION
EEPROM devices belong to two categories: page programmable memories and word programmable memories. A word generally represents a byte (8 bits), and a page generally represents a set of words belonging to a same word line. Page programmable memories require a high number of programming latches. More particularly, they require as many programming latches as there are bit lines to ensure a simultaneous programming of all the words of a page. In contrast, word programmable memories require a reduced number of latches, for example, eight programming latches for a byte programmable memory.
FIG. 1
schematically illustrates the conventional architecture of a memory MEM
1
of the second type, i.e., one that is programmable by word. The memory comprises word lines WL
i
, bit lines BL
j
arranged in columns COL
k
, with each illustrated column comprising eight bit lines BL
0
to BL
7
, and memory cells CE
i,j
. The memory cells CE
i,j
are arranged in an array and are connected to the word lines WL
i
and the bit lines BL
j
.
Each cell CE
i,j
comprises a floating gate transistor FGT and an access transistor TA. The access transistor TA has its gate G connected to a word line WL
i
, its drain D connected to a bit line BL
j
, and its source S connected to the drain D of transistor FGT. Transistor FGT has its gate G coupled to a column selection line CL
k
by a gate control transistor CGT
i,k
, and its source S is connected to a source line SL
i
. The gate of transistor CGT
i,k
is connected to word line WL
i
.
Thus, each group of eight cells CE
i,j
connected to a word line WL
i
and to the bit lines BL
0
to BL
7
of a column COL
k
forms a word W
i,k
that may be selected by the corresponding column selection line CL
k
and word line WL
i
. To this effect, the word lines WL
i
are connected to the outputs of a line decoder RDEC. The column selection lines CL
k
are connected to latches LSC
k
delivering a gate control signal CGS
k
which depends on a column selection signal SEL
k
received as an input. The selection signal SEL
k
is delivered by a column decoder CDEC. Line decoder RDEC and column decoder CDEC receive respectively the most significant bits and the less significant bits of an address AD applied to the memory. Source line SL
i
may be brought to a floating potential or may be connected to ground by a transistor SLT driven by a signal SLS.
Memory MEM
1
also comprises eight programming latches LP
0
to LP
7
, the outputs of which are connected to lines L
0
to L
7
, and eight sense amplifiers SA
0
to SA
7
, the inputs of which are connected to the lines L
0
to L
7
by read transistors TR
0
to TR
7
driven by a signal READ. The outputs of amplifiers SA
0
to SA
7
and the inputs of latches LP
0
to LP
7
are connected to a data bus DTB, allowing data read in the memory to be delivered by amplifiers SA
0
to SA
7
or data to be programmed in the memory to be loaded into programming latches LP
0
to LP
7
.
Lines L
0
to L
7
are coupled to the bit lines BL
0
to BL
7
of each column COL
k
by a multiplex bus DMB. Each programming latch LP
j
of rank j is thus connected to the bit lines of the same rank j present in the columns. To ensure a selective connection of the output of a latch or of the input of a sense amplifier to a predetermined bit line, each bit line BL
0
-BL
7
of each column COL
k
is provided with a selection amplifier or transistor TSBL
0
to TSBL
7
. Selection transistors TSBL
0
to TSBL
7
of the bit lines of a same column COL
k
are driven by a common selection signal BLS
k
, delivered by a latch LSBL
k
receiving as an input a column selection signal SEL
k
coming from column decoder CDEC.
There can thus be found in each column of rank k of memory MEM
1
a column selection latch LSC
k
and a bit lines selection latch LSBL
k
which are driven by a common column selection signal SEL
k
coming from column decoder CDEC. These latches deliver a gate control signal CGS
k
and a bit line selection signal BLS
k
. The values of these signals depend on the current operating phase, that is, erasure, programming or reading of a cell.
An erasing or programming operation of a memory cell includes injecting or extracting electrical charges by the Fowler Nordheim effect in the floating gate of the transistor FGT of the cell. An erased transistor FGT has a positive threshold voltage VT
1
, and a programmed transistor FGT has a negative threshold voltage VT
2
.
When a reading voltage Vread between VT
1
and VT
2
is applied to its gate, an erased transistor remains turned OFF, which corresponds by convention to a logic 1, and a programmed transistor is turned ON, which corresponds by convention to a logic 0. The erasing operation is performed by applying an erasing voltage Vpp on the order of 12 to 20 V to the gate G of transistor FGT while source line SL
i
is brought to ground. The programming operation is performed by applying a programming voltage Vpp to the drain D of transistor FGT by an access transistor TA, while its gate is brought to ground.
During an erasing phase of the memory cells of a word W
i,k
, the latch LSC
k
and the latch LSBL
k
of the concerned column are activated by signal SEL
k
. Latch LSC
k
delivers a gate control signal CGS
k
equal to Vpp, and latch LSBL
k
delivers a voltage equal to zero (ground). During a programming phase of the memory cells of word W
i,k
, latch LSC
k
delivers a voltage equal to zero (ground) and latch LSBL
k
delivers voltage Vpp so that the transistors TSBL
0
to TSBL
7
of the column are turned ON and couple the outputs of the programming latches LP
j
to the bit lines of the column. During a reading phase of word W
i,k
, latch LSC
k
delivers a reading voltage Vread and latch LSBL
k
delivers a voltage Vcc so that the transistors TSBL
0
to TSBL
7
of the column are turned ON and couple the inputs of the sense amplifiers SA
j
to the bit lines of the column. Read transistors TR
j
are also turned ON and signal READ is at 1.
As mentioned above, the advantage of such a memory is to have a small number of programming latches, such as the eight latches LP
0
to LP
7
, for example, when a page programmable memory comprises as many programming latches as bit lines. The providing of transistors TSBL
0
to TSBL
7
is necessary to ensure the connection of a programming latch to a predetermined bit line. The providing of transistors TSBL
0
to TSBL
7
implies the providing of the latches LSBL
k
to drive such transistors.
In other words, the bit line selection latches LSBL
k
make it difficult to reduce the number of programming latches, and complicates the structure of the memory. Thus, for example, a word programmable memory comprising 2048 bit lines arranged in 256 columns must be provided with 256 column selection latches and 256 bit lines selection latches. The latches each comprise a locking element of the selection signal SEL
k
so that the delivered signals CGS
k
and BLS
k
remain stable until a reset signal is applied to the latches.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to simplify the architecture of a EEPROM device. The present invention is based on the observation that the locking element comprised in a column selection latch can be used to generate and/or control the selection signal of the bit lines of the column, in addition to the gate control signal provided for the floating gate transistors.
This and other objects, advantages and features according to the present invention are provided by integrating, in a same latch comprising one locking element only, the column selection function and the bit lines selection function. The latch includes two outputs, one for delivering the gate control signal and the other for delivering the bit lines selection signal.
More particularly, the present invention provides an electrically programmable and erasable memory
Bertrand Bertrand
Chehadi Mohamad
Naura David
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Hur J. H.
Jorgenson Lisa K.
Lebentritt Michael S.
STMicroelectronics SA
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