Word oriented high speed buffer memory system connected to a sys

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G06F 1300

Patent

active

042143039

ABSTRACT:
A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.

REFERENCES:
patent: 3820078 (1974-06-01), Curley et al.
patent: 3840862 (1974-10-01), Ready
patent: 3840863 (1974-10-01), Fuqua et al.
patent: 3866183 (1975-02-01), Lange
patent: 4068299 (1978-01-01), Bachman

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