Word line transistor stacking for leakage control

Details Word line transistor stacking for leakage control Word line transistor stacking for leakage control

2005-07-05

2005-07-05

Tran, Michael (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S129000

Reexamination Certificate

active

06914848

ABSTRACT:
A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.

REFERENCES:
patent: 6781892 (2004-08-01), Hsu et al.
patent: 6801456 (2004-10-01), Hsu et al.

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