Word line straps using two different layers of metal

Details Word line straps using two different layers of metal Word line straps using two different layers of metal

2000-02-07

2001-07-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230060

Reexamination Certificate

active

06266264

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly, to a DRAM wherein more than one layer of metalization is used in strapping polysilicon word lines.
2. Description of the Related Art
Semiconductor dynamic random access memory (DRAM) devices or systems using dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static random access memory (SRAM) cells (e.g., 6-transistor (6T cells), or 4-transistor/2-resistor (4T/2R) cells). Such DRAM arrays historically have had lower performance than SRAM arrays. Consequently, system designers typically have chosen DRAM arrays when high density and low cost are required, such as for CPU main memory applications. Conversely designers typically have chosen SRAM arrays when higher performance is required, such as for cache memory and high speed buffer applications.
The reasons often cited for the lower performance of DRAM include: the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays); resulting in the need to restore data back into each sensed memory cell during the active cycle; the need to equilibrate bit lines and various other differential nodes; the need to precharge various circuit nodes between active cells; the need to bootstrap the selected word line above the supply voltage; the delay along the length of the word line and the requirement for periodic refreshing of all dynamic memory cells.
Generally, the memory cells are interconnected by bit lines or columns and word lines or rows. These lines are defined in a polysilicon layer of the memory device. Word lines implemented only in polysilicon layers, however, often have unacceptable delays in signal propagation, especially when high speed operation is desired.
In DRAMs, attempts to improve performance with word line strapping are limited by the fact that polysilicon word lines may be placed closer together (“pitched”), than metal lines may be “pitched.” One approach to overcome this pitch problem in DRAMs includes providing a row decoder with a metal “word line” for every four rows. Local final decoders distributed along the metal “word line” drive a selected one of four relatively short polysilicon word lines when its metal “word line” is selected. By using such a row decoder with distributed final decoders, smaller transistors need to be used in the final decoders because there is not enough room for larger transistors. Therefore, while this solution may improve performance, it is still generally slow with regard to many of today's applications.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, a word line structure in a memory device includes a polysilicon layer, a first metal layer, and a second metal layer. The polysilicon layer is configured into word lines. Half of the polysilicon word lines are strapped to corresponding word lines defined in the first metal layer, while the remaining polysilicon word lines are strapped to corresponding word lines defined in the second metal layer.
By strapping word lines in the relatively high resistance polysilicon layer to word lines in the very low resistance metal layers, signal propagation delays in the word lines are significantly reduced. Additionally, implementing the word line structure using two different layers of metal allows the polysilicon word lines to be spaced at the minimum possible distance apart using the design rules of the semiconductor manufacturing process, and also allows the metal strapping of the word lines to use somewhat relaxed design rules, yet does not require any distributed buffers or final decode buffers.
In another embodiment of the present invention, polysilicon word lines are grouped in adjacent pairs. The pairs are alternatingly strapped in the first metal layer and the second metal layer, i.e., a first word line pair consisting of two adjacent polysilicon word lines are strapped by the first metal layer while a second polysilicon word line pair adjacent to the first word line pair is strapped by the second metal layer. Such an arrangement allows for coordination with row redundancy capability, which in one embodiment replaces word lines in adjacent pairs. Because short circuits within a layer are more common than short circuits between layers, the efficiency of the limited number of redundant rows is enhanced. Thus, with this arrangement, a row to adjacent row short in either metal layer or in the polysilicon layer has a 50% chance of causing a failure in two rows that would be replaced together anyway.
Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred embodiments below, in conjunction with reference to the drawings, in which like numerals represent like elements.


REFERENCES:
patent: 4693925 (1987-09-01), Cheung et al.
patent: 5768186 (1998-06-01), Ma
patent: 5940315 (1999-08-01), Cowles

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