Word line selection circuit for static random access memory

Details Word line selection circuit for static random access memory Word line selection circuit for static random access memory

1996-03-12

1998-04-07

Zarabian, A.

Static information storage and retrieval

Powering

36518909, 36523006, G11C 700

Patent

active

057372756

ABSTRACT:
The semiconductor memory device disclosed has a boost circuit, a word drive circuit and a row decoder, and includes a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor, and a second N-channel MOS transistor. The first P-channel MOS transistor and the second P-channel MOS transistor have drains and gates cross-connected and each source and a substrate connected to an output terminal of the boost circuit. The first N-channel MOS transistor has a drain connected to the drain of the first P-channel MOS transistor, a source connected to a ground terminal, and a gate connected to an output terminal of the row decoder. The second N-channel MOS transistor has a source connected to the output terminal of the row decoder, a drain connected to the drain of the second P-channel MOS transistor, and a gate receiving one of a power supply voltage and a control signal. The gate of the N-channel word driver can be driven directly from the row decoder whereby the select and non-select ratio is improved.

REFERENCES:
patent: 5406523 (1995-04-01), Foss
patent: 5550504 (1996-08-01), Ogihara
M. Ukita et al.; "A Single-Bit-Line Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAM's"; IEEE Journal of Solid-State Circuits, vol. 28, no. 11, Nov. 1993; pp. 1114-1118.

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