Word line non-boosted dynamic semiconductor memory device

Details Word line non-boosted dynamic semiconductor memory device Word line non-boosted dynamic semiconductor memory device

1998-09-24

2000-07-11

Zarabian, A

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

060882867

ABSTRACT:
A memory array is divided into memory blocks each including a predetermined number of rows, and voltages on storage nodes are boosted by changing cell plate voltages in the memory block including a selected word line. An unselected word line is held at a negative voltage level when the selected word line is driven to a power supply voltage level. Thereby, it is possible to prevent movement of charges due to connection of a bit line with the storage node at the time of change in cell plate voltage of an unselected memory cell, and destruction of data in the unselected memory cell can be prevented. A dynamic semiconductor memory device not requiring a boosted voltage is provided.

REFERENCES:
patent: 5898608 (1999-04-01), Hirano
patent: 5905685 (1999-05-01), Nakamura
"A Storage-Node-Boosted RAM with Word Line Delay Compensation", K. Fujishima et al., 1982 IEEE International Solid-State Circuits Conference, pp. 66-67.

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