Word-line driving circuit with reduced current leakage

Details Word-line driving circuit with reduced current leakage Word-line driving circuit with reduced current leakage

2002-03-27

2003-09-16

Tran, M. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290

Reexamination Certificate

active

06621743

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a word-line driving circuit for a non-volatile semiconductor memory.
2. Description of the Related Art
A semiconductor memory includes a plurality of word lines, each coupled to a plurality of memory cells. In normal read and write operations, one of the word lines is selected and driven, and the memory cells coupled to the driven word line are accessed. Some types of non-volatile semiconductor memory, such as flash memory, also perform a chip erase operation, in which all the word lines are driven at once and the data in all the memory cells in the memory device are erased simultaneously.
In a conventional word-line driving circuit for a non-volatile semiconductor memory, each word line is coupled through a first switching element to a signal line that provides various voltages used for reading, writing, and erasing data, and through a second switching element to ground. When the word line is driven, the first switching element is switched on, and the second switching element is switched off. When the word line is not driven, the first switching element is switched off and the second switching element is switched on.
The switching elements are typically metal-oxide-semiconductor field-effect transistors. Even when switched off, these transistors do not block current flow completely; a small subthreshold current leaks through, the amount depending on the source-drain potential difference and the ambient temperature. In a chip erase operation, in which the drain potential of the second switching elements is comparatively high, the total amount of current that leaks through the second switching elements to ground can become large enough to lower the power-supply voltage. Even if the device is designed so that this effect is negligible at normal temperatures, if the chip erase operation is performed under high-temperature conditions, the leakage current may increase to the point where the power-supply voltage is significantly reduced. This reduction of the power-supply voltage in turn reduces the voltages generated from the power-supply voltage, including the voltage used to erase the memory-cell data. A resulting problem is incomplete erasure of the data.
Further explanation of this problem will be given in the detailed description of the invention.
A similar problem can occur in block erase operations, in which the data in the memory cells coupled to a selected group of word lines are erased simultaneously.
SUMMARY OF THE INVENTION
An object of the present invention is to reduce current leakage when the memory cells coupled to a plurality of word lines in a non-volatile semiconductor memory are erased simultaneously.
Another object is to increase the reading speed of a non-volatile semiconductor memory.
The present invention provides both a method of driving the word lines in a non-volatile semiconductor memory, and word-line driving circuits employing the invented method.
The non-volatile semiconductor memory to which the invention pertains has a plurality of memory cells coupled to different word lines. The word lines are selectively driven to different potentials to read, write, and erase data stored in the coupled memory cells. In particular, the data in the memory cells coupled to some or all of the word lines can be erased simultaneously by driving those word lines to an erasing potential.
The word lines are coupled to respective switching elements through which a ground potential is supplied to the word lines that are not driven to one of the above potentials for reading, writing, or erasing. When a plurality of word lines are driven simultaneously to the erasing potential, a mitigating potential is supplied to their respective switching elements, which are switched off. The mitigating potential is intermediate between the ground potential and the erasing potential.
Supply of the mitigating potential, instead of the ground potential, reduces the voltage applied across the switched-off switching elements when a plurality of word lines are driven simultaneously to the erasing potential, thereby reducing current leakage through the switching elements.
The erasing potential may be generated by level-shifting a write control signal. A reading potential may be generated by logic operations, without level shifting, and used to drive the word lines when data are read. The elimination of level-shifting delays can speed up the reading of the data.


REFERENCES:
patent: 6111792 (2000-08-01), Oku et al.
patent: 6490201 (2002-12-01), Sakamoto
patent: 6504758 (2003-01-01), Sacco et al.
patent: 11185489 (1999-07-01), None

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