Word line driving circuit

Details Word line driving circuit Word line driving circuit

2002-12-23

2004-09-14

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110

Reexamination Certificate

active

06791897

ABSTRACT:

TECHNICAL FIELD
The present disclosure relates generally to memory devices, and more particularly, to a word line driving circuit in a memory device.
BACKGROUND
Generally, memory cells are arranged in a matrix scheme and enabled one by one with a word line signal. That is, if an active command is inputted from the outside, a word line of a corresponding address is enabled. To enable the word line, a hierarchical driving method is usually used. In the memory cell array as shown in
FIG. 1
, for example, a word line driving circuit decodes 64 main word line driving signals (HBMWB<
0
:
63
>) and 8 driving signals (HAMWB<
0
:
7
>) to enable one of 512 word lines.
The main word line driving circuit shown in
FIG. 2
includes three NMOS transistors MN
1
, MN
2
and MN
3
serially connected to two PMOS transistors MP
1
and MP
2
, and two inverters IV
1
and IV
2
. A circuit for controlling the main word line driving circuit is shown in FIG.
3
. The operation of the conventional main word line driving circuit is described below with reference to
FIGS. 3 and 4
.
When an active command is inputted, an output signal (MWPREB) of an AND gate A
1
shown in
FIG. 3
becomes a HIGH state and precharge is released if inactive signals (INACTV
1
and INACTV
2
) becomes a HIGH state and a block select signal (BLKSEL) becomes a HIGH state. Also, when each of a signal (X
345
<
0
:
7
>) resulting from an address (A
3
,
4
,
5
) being decoded, a signal (X
678
<
0
:
7
>) resulting from an address (A
6
,
7
,
8
) being decoded, and a signal (X
9101112
) resulting from an address (A
9
,
10
,
11
,
12
) being decoded is at a HIGH state, a PMOS transistor MP
1
shown in
FIG. 2
is turned off and NMOS transistors MN
1
, MN
2
, MN
3
are turned on. Therefore, the main word line driving signal (HBMWB) being an output of the inverter (IV
2
) is enabled to a LOW state. Next, when a precharge command is inputted, the main word line driving signal (HBMWB) is precharged with a HIGH state if each of the decoded signals (X
345
, X
678
, X
9101112
) is disabled to a LOW state and the output signal (MWPREB) becomes a LOW state. Thereafter, the main word line driving signal (WL) maintains the HIGH state with it being precharged.
Referring to
FIG. 5
, if the power supply line are positioned between the lines for the main word line driving signal, the operating speed of the memory is improved because drop in the voltage is reduced by the power supply line. In a common DRAM, a characteristic of tRCD can be improved by about two nanoseconds.
However, if there is resistive connection between the lines for the main word line driving signal and the power supply line because of problems in the process, a VPP level being an internally generated power is lowered by the resistive connection between VPP being a voltage level of HBMWB<
1
> at a precharge state and the power supply line VDD even though a corresponding word line driving signal is substituted by a redundancy main word line driving signal (RHBMWB<
0
>) as indicated by “A” in FIG.
5
. Generally, VPP has a value of 4V and VDD has a value of 3V. In this case, a VPP level sensor and a pump circuit are driven to raise the level of the lowered VPP power supply. A problem occurs when the yield of the memory is significantly lowered because there is a lot of current flow at the precharge state.
SUMMARY OF THE DISCLOSURE
The present disclosure provides a main word line driving circuit capable of suppressing an increase in current flow at a precharge state in such a way that a main word line driving signal is substituted by a redundancy main word line driving signal and a corresponding main word line driving signal is floated when a line for a main word line driving signal and a neighboring power supply line are connected.
The word line driving circuit includes a main word line driving circuit configured to generate a word line driving signal, pull-up and pull-down transistors serially connected to each other, and a control circuit configured to generate a control signal to control the word line driving signal, to turn off the pull-up transistor and to turn on the pull-down transistor in response to an active, to enable the word line driving signal to a LOW state, to turn on the pull-up transistor and to turn on the pull-down transistor for a given period of time in response to a precharge command, to precharge the word line driving signal to a HIGH state, and to turn off the pull-up transistor and the pull-down transistor to float the word line driving signal after the precharge command.
Further, the word line driving circuit comprises a control circuit configured to output a driving signal, a main word line precharge control signal, a block select signal, and first, second and third control signals; a delay circuit configured to delay the block select signal; a first PMOS transistor connected between the power supply and a first node; a first NMOS transistor responsive to the main word line precharge control signal; first, second and third NMOS transistors serially connected to each other between the first node and the ground, and responsive to the first, second and third control signals, respectively; a pull-up transistor connected between the power supply and an output node; a pull-down transistor connected between the output node and the ground; an inverter connected between a gate terminal of the pull-down transistor and the first node; a second PMOS transistor connected in parallel to the first PMOS transistor, wherein a gate terminal of the second PMOS transistor is connected to a gate terminal of the pull-down transistor; and a NAND gate configured to logically combine an output signal of the delay circuit and the potential of the first node to provide the logically combined signal to a gate terminal of the pull-up transistor.


REFERENCES:
patent: 5406526 (1995-04-01), Sugibayashi et al.
patent: 5864508 (1999-01-01), Takashima et al.
patent: 6144610 (2000-11-01), Zheng et al.
patent: 2002/0054530 (2002-05-01), Chung et al.

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