Word line driver for semiconductor memories

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365 63, 36518911, G11C 800

Patent

active

06011746&

ABSTRACT:
A hierarchical word line driving structure uses a shared inverter circuit architecture which allows for lower power consumption and a pulsed control signal to ensure accurate memory retrieval. The shared inverter word line structure includes a row decoder, a first sub-word line driver, a second sub-word line driver, and an interconnect line. The first sub-word line driver includes an inverting circuit for inverting the signal propagating along the global word line, while the second sub-word line driver does not. The interconnect line is coupled between the first and second sub-word line drivers to communicate the inverted signal therebetween. A pulsed control signal is supplied to clamping transistors connected to unselected word lines to ensure they remain clamped to ground.

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