Word line driver for semiconductor memories

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365 72, 365 63, G11C 800

Patent

active

058751491

ABSTRACT:
A hierarchical word line driving structure is disclosed that uses a single global word line and low power sub-word line driver circuits that are relatively small in size. Higher density memory cell arrays are made possible by inverting the signal on a global word line inside each sub-word line driver circuit.

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