Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-03-29
2003-11-11
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080, C365S189110, C326S105000, C326S106000
Reexamination Certificate
active
06646949
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to scaled down dynamic random access memory (RAM) cells which operate with a negative word line voltage. Specifically, a word line driver circuit is described which employs a two-state stage pull-down process for resetting the word line voltage to a negative potential.
Increasing DRAM cell density requires that each cell feature size be reduced. The reduction in cell size requires a corresponding reduction in the MOSFET device sizes which provide one bit data storage. Practical limitations are imposed on the MOSFET size because a reduced gate insulator thickness reduces the reliability of the device, and the threshold voltage must remain sufficiently high to maintain the channel conduction OFF. These limits are reached when MOSFET device feature sizes of 150 nm and smaller are fabricated.
Reduction of the MOSFET threshold voltage Vt has been achieved using a negative word line off voltage such as −0.5 volts to hold the device in a nonconducting state. With the use of a negative world line off voltage, the smaller device with a reduced Vt may be used which also requires a lower voltage Vth for setting a bit level on the DRAM cell.
Channel doping requirements for a MOSFET device using a negative word line off voltage are also reduced. The corresponding reduction in channel doping reduces junction leakage for the storage device, thus improving the data retention time for the device.
Problems occur in resetting the word line voltage from a positive writing voltage to an OFF state wherein the word line is returned to the negative bias voltage. The word line must be driven from the positive voltage to the negative level without generating a voltage bounce on adjacent word lines which are also connected to the same negative bias voltage source. As the negative bias voltage source tends to have a higher impedance, the word line discharge will cause a local voltage increase (i.e., voltage bounce) on the negative word line voltage source which is coupled to other word lines. The inadvertent coupling of the voltage bounces occurring from one line to adjacent lines will tend to reduce the stored data charge on the adjacent cells which are written with the adjacent word lines. The problem is exacerbated when the array of word lines is subject to addressing patterns which cause repeated local voltage bounces coupled to adjacent word lines.
A word line driver has been disclosed in U.S. Pat. Nos. 5,650,976 and 5,410,508 which seeks to avoid the foregoing problems by discharging the word line in two stages. During a first stage of discharge, the word line is connected to ground through a PMOS transistor, which discharges the word line until the voltage across the PMOS transistor reaches approximately 0.65 volts. During a following second discharge phase, the word line is connected through an NMOS transistor to a negative potential which further discharges the word line to a lower potential.
The two state process described in the foregoing patents has some disadvantages associated with it. The first is that the PMOS transistor is connected back through a relatively high impedance path to ground which decreases the speed of discharge. The discharge time is reduced by reducing the device threshold voltage. However, the lower threshold voltage devices have an increased leakage current, and the gate of the PMOS and NMOS transistor must be driven to the Vneg voltage which requires a larger voltage swing on the gates of these transistors. The larger voltage swing severely stresses the transistor gates which can reduce the device reliability.
A further disadvantage may result when word lines are half selected which forces the PMOS transistor to turn on and allow a d.c. current to flow and reduce the Vneg voltage. Any short term reduction of the Vneg potential will result in the charge on the memory cell capacitor being reduced thus impairing the integrity of the stored data.
The present invention is directed to a circuit for minimizing the voltage bounce when returning a word line to a negative OFF voltage potential using a two stage pull down process which avoids these disadvantages.
SUMMARY OF THE INVENTION
A word line driver is provided for a row of memory elements of a dynamic random access memory. Each of the transistor memory elements have an associated storage capacitor, and a word line is connected to the gate of the transistor of a row of memory elements for enabling charging of the storage capacitor of each memory element. A first transistor of the word line driver is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode connects the word line to a first selector signal which forward and reverse biases the diode, alternately permitting the word line to be connected to ground. A second transistor drives the word line to a positive potential in response to a second selector signal. When the word line is deselected, the second transistor conducts the positive potential from the word line, and the diode initially conducts current, bringing the word line to substantially zero volts. The first transistor then brings the word line potential to a negative potential. By employing a two-stage process for resetting the word line, first to ground and then to a negative potential, a voltage bounce which occurs along the bus carrying the negative potential is reduced.
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Ellis Wayne F.
Hsu Louis L-C.
Mandelman Jack A.
Tonti William R.
Connolly Bove & Lodge & Hutz LLP
Ho Hoai
Yoha Connie C.
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