Word line driver for DRAM embedded in a logic process

Details Word line driver for DRAM embedded in a logic process Word line driver for DRAM embedded in a logic process

2007-09-25

2007-09-25

Pham, Ly Duy (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S072000, C365S174000, C365S189090, C365S189110, C365S227000

Reexamination Certificate

active

11166856

ABSTRACT:
A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

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