Word line driver circuitry and methods for using the same

Details Word line driver circuitry and methods for using the same Word line driver circuitry and methods for using the same

2007-09-11

2007-09-11

Pham, Ly D. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S063000, C365S194000

Reexamination Certificate

active

10971939

ABSTRACT:
Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time delay prevents DOUT_BAR from changing its state immediately after DOUT changes state. As result, both the first and second transistors are turned ON at the same time for a predetermined of time. It is during this time that the voltage on the word line is rapidly driven to a LOW voltage. When the second transistor turns OFF, high impedance circuitry limits the flow of leakage current. This minimizes leakage current when the word line is OFF and when short circuit conditions are present between two or more word lines or between a word line and a bit line.

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patent: 130793 (1985-01-01), None

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