Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-05-05
2001-09-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S230060, C365S189040
Reexamination Certificate
active
06285593
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to non-volatile semiconductor memories, and more particular, to the operation of such memories to increase the available threshold voltage window size.
2. Description of Related Art
Non-volatile semiconductor memories such as EPROMs, EEPROMs, and Flash memories are well known. In such memories, a threshold voltage Vt of a memory cell indicates a data value stored in the memory cell. When writing (programming) to a selected memory cell in a conventional non-volatile memory array, programming voltages are applied via a word-line (WL) connected to a control gate of the selected cell, via a bit-line (BL) connected to a drain of the selected cell, and a via source-line (SL) coupled to a source of the selected cell. The combination of programming voltages changes the threshold voltage of the selected cell, typically by causing Fowler-Nordheim (F-N) tunneling or channel hot electron (CHE) injection which charges (or discharges) a floating gate in the selected memory cell.
For example, to induce CHE injection in a selected memory cell containing a typical N-channel floating gate transistor, a high voltage Vpp (e.g., approximately 9 to 12 volts or higher) is applied as the control gate voltage Vg to the WL containing the selected cell, a high voltage (e.g., approximately 4.5 to 5.5 volts or higher) is applied as the drain voltage Vd to the BL containing the selected cell, and a low voltage (e.g., near 0 volt) is applied as the source voltage Vs to the SLs. Hot electrons are injected into the floating gate to increase the threshold level with respect to the control gate, thereby programming the selected cell. By adjusting the programming voltage Vpp and/or programming pulse width Twp, the selected cell can be programmed to a desired threshold voltage Vt.
It is desirable to have the ability to program a wide range of threshold voltages for each memory cell in a memory array for wider Vt windows. Wider Vt windows improve the resolution and signal-to-noise ratio (SNR) for a given number of levels of storage and increase the number of levels of storage for a given resolution or Vt increment per level. This translates to improved dynamic range, SNR, reliability, and data integrity for analog/multi-level and multi-bit-per-cell memories.
However, certain practical constraints limit the amount that a Vt window can be widened. For conventional memories, typical threshold voltages have maximum values of approximately 6 volts and minimum values of approximately 3 volts, which represents typical Vt windows of about 3 volts.
During a write to a selected memory cell, the high bit-line and word-line voltages for the selected memory cell can create large voltage differences between the floating gate and drain of unselected memory cells and thereby induce Fowler-Nordheim tunneling that disturbs the threshold voltages of these unselected memory cells by causing electrons to tunnel out or escape from the floating gate to drain. The voltage difference between the drain and floating gate of an unselected memory cell subjects the memory cell to a disturb referred to herein as drain disturb. Since the Fowler-Nordheim tunneling current is exponentially dependent on the electric field in the gate oxide between the bit-line and floating gate, drain disturb will worsen significantly even with a small increase in the electric field.
Consequently, the maximum Vt is limited by program disturb (or drain disturb) of a previously programmed cell. The total accumulative disturb (in mV) is dependent on the number of cells on a bit-line, the write time of a cell, the area and gate oxide thickness between the drain and the floating gate, and the drain voltage applied for programming. For example, drain disturb can be reduced by decreasing bit-line lengths by arranging memory cells in several small arrays rather than one large array. With smaller arrays, fewer memory cells are on the same column so that programming a selected memory cell disturbs fewer unselected memory cells. However, smaller arrays require more source-line, word-line, and bit-line decoders, which increases the cost and size of the memory system. Typical practical considerations limit the maximum Vt to about 6V. Minimum threshold voltages are usually limited by leakage current of erased and unselected memory cells coupled to the same bit-line as the selected memory cell. During a read or verify operation, typically 0 volts or ground is applied as the control gate voltage Vg to unselected WLs, i.e., WLs that do not contain the selected cell, and a ramped voltage is applied as the control gate voltage Vg to the selected WL for a read operation and a verify voltage proportional to the desired programmed threshold voltage is applied as the control gate voltage Vg to the selected WL for a verify operation.
During a read operation, the voltage applied to the control gate of the selected cell is ramped until the selected memory cell conducts, i.e., when the voltage at the control gate is at or exceeds the threshold voltage of the cell. The voltage at which the cell conducts represents the voltage stored in the cell. However, erased cells in the same column as the selected cell may contribute sufficient leakage current to the bit-llie of the selected cell and cause errors during read or verify operations.
Memory cells in conventional Flash memory arrays are typically simultaneously erased, so that all of the cells in the array connected to a common source line are simultaneously erased. Memory cells are erased by discharging the floating gate, which is typically accomplished through Fowler-Nordheim tunneling by creating a large positive voltage from the source to the gate of the floating gate transistor, while floating the drain. This positive voltage can be as much as 12 volts. Suitable voltages, which are well known, are applied to the WLs, BLs, and SLs of the array to supply voltages to the control gate, drain, and source, respectively, of memory cells in the array. These voltages cause electrons to tunnel from the floating gate to the source via Fowler-Nordheim tunneling, thereby returning the cell to an erased state.
However, erase characteristics of non-volatile memory cells are typically somewhat random and difficult to control. The key controllable parameters include erase voltage, erase time, and the number of cells in a sector which are erased together. In Flash arrays, cells connected to a common source line are erased for the same amount of time. Ideally, each cell in the array requires the same amount of time to erase, i.e., to remove electrons from floating gate and achieve the same lower selected threshold voltage. However, practically, individual memory cells have slightly different characteristics, which require slightly different erase conditions to achieve the same erased threshold voltage Vte. Thus, even with existing erase and Vt monitor algorithms, some faster cells may become over-erased, which can potentially generate excessive positive charge on the floating gate and excessively lower the erased Vt (Vte) of the memory cell. In some situations of over-erasing, the erased threshold voltage becomes negative. As a result, even when 0 volts is applied to the control gates during reading or verify, over-erased cells will conduct slightly and supply a current sufficient to the bit-lines coupled to the over-erased cells, thereby potentially giving an erroneous reading.
The leakage current conducted by over-erased cells in a column during a read or verify operation can degrade or destroy the memory's reliability and endurance. Ideally, the only cell in the column biased for possible conduction is the cell in the selected word line WL. However, if any of the cells in the selected bit-line or column are over-erased and conduct significant current (i.e., sub-threshold conduction current), the combined current flow in the bit-line may exceed the threshold for reading or verify, thereby yielding erroneous results. In some severe situations, a single over-erased cell disables the
Le Thong
Nelms David
SanDisk Corporation
Skjerven Morrill & MacPherson LLP
LandOfFree
Word-line decoder for multi-bit-per-cell and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Word-line decoder for multi-bit-per-cell and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Word-line decoder for multi-bit-per-cell and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2470954