Word line decoder for dual-port cache memory

Details Word line decoder for dual-port cache memory Word line decoder for dual-port cache memory

1999-12-23

2001-03-06

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230050

Reexamination Certificate

active

06198684

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to memory decoders, and in particular to decoders for a dual port cache memory.
DISCUSSION OF THE RELATED ART
An example of prior art decoders is shown in FIG.
1
. In this example, cache memory
190
has 64 rows of memory cells. Therefore, the memory address of each row can be represented by six bits. Exemplary cell
150
of memory
190
is associated with two decoders
111
,
112
that enable two corresponding drivers
121
,
122
to drive corresponding word lines
131
,
132
in order for a first or a second device to read the contents of memory cell
150
.
Decoder
111
receives a memory address through bus
101
from a first device that wants to read from cache memory
190
. Three of the address bits are received by first stage AND gate
141
and the other three bits are received by first stage AND gate
151
. The outputs of the first stage AND gates
141
,
151
are received by second stage AND gate
161
. A second decoder
112
is required to receive a memory address through data bus
102
from a second device that wants to read from memory
190
.
FIG. 2
shows a circuit diagram of AND gates
141
,
151
and
161
. AND gate
141
receives bits
0
through
2
of memory address
101
. Transistors
200
,
201
and
202
are connected in series. Similarly, the transistors of AND gates
151
and
161
are also connected in series.
One disadvantage of the prior art decoders is that the transistors in each of the AND gates are connected in series, which causes a delay time in reading from memory
190
. Another disadvantage in the prior art is that a dual port cache memory employs two completely separate and independent decoders. Furthermore, the decoders are multi-staged AND gates. As a result, the decoders consume a significant amount of area, leading to higher design overhead.
SUMMARY OF THE INVENTION
In one embodiment, a memory cell having a first port and a second port is provided. A first word line is associated with the first port, and a second word line is associated with the second port. A first driver is associated with the first word line, and a second driver is associated with the second word line. A decoder is associated with the first and second drivers.


REFERENCES:
patent: 5317536 (1994-05-01), Aoyama
patent: 5335199 (1994-08-01), Aoyama
patent: 5812486 (1998-09-01), Shinmori
patent: 6005794 (1999-12-01), Sheffield et al.

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