Word line clamping circuit and decoder

Details Word line clamping circuit and decoder Word line clamping circuit and decoder

1976-03-08

1978-02-14

Hecker, Stuart N.

Static information storage and retrieval

Addressing

365189, G11C 700

Patent

active

040742377

ABSTRACT:
A word line clamping circuit for use with field effect transistor memories is disclosed which permits the clamping of the word line to a reference potential using a minimum of devices and without the consumption of d.c. power so that multi-level bit line potentials may be utilized during the memory cycle. This is achieved by connecting a field effect transistor (FET) between word line and ground under control of a word line decoder so that a node associated with the last mentioned FET is held in either an uncharged or charged condition depending on whether the decoder is selecting its associated word line or not selecting it. Because the unselected word lines are held at ground during a portion of the memory cycle when reading or writing of memory cells associated with a selected word line is taking place, any capacitive coupling which might change the content of cells associated with unselected word lines is avoided and, for whatever the reason, bit line potentials may now be changed to different levels without affecting information storage during the memory cycle. Two circuits are shown which, under control of the word line decoder, permit the grounding of unselected word lines during at least a major portion of the memory cycle.

REFERENCES:
patent: 3644904 (1972-02-01), Baker
patent: 3909806 (1975-09-01), Uchida
Anderson et al., Decoding Scheme for MOS Random-Access Memories, IBM Technical Disclosure Bulletin, vol. 17, No. 10, 3/75, pp. 2832-2833.

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