Word line activation in memory devices

Details Word line activation in memory devices Word line activation in memory devices

2007-11-27

2011-11-01

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185130, C365S185170, C365S185180

Reexamination Certificate

active

08050102

ABSTRACT:
Memory devices and methods facilitate flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control bus. By identifying the address space to which a word line belongs, its appropriate configuration control bus may be selected and the control signals from the selected bus used to select the appropriate potentials for driving the word lines.

REFERENCES:
patent: 6044017 (2000-03-01), Lee et al.
patent: 2005/0141283 (2005-06-01), Lee et al.
patent: 2006/0245260 (2006-11-01), Kim
patent: 2007/0147118 (2007-06-01), Pham et al.

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