Word decoder for a memory array

Details Word decoder for a memory array Word decoder for a memory array

1989-10-30

1991-06-04

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365177, 307449, 307463, G11C 700, G11C 800, H03K 19094

Patent

active

050220101

ABSTRACT:
A word decoder for a memory array includes a decode NOR/OR circuit 52 coupled to an output driver circuit 54. Decode NOR/OR circuit 52 includes a plurality of input signals IN1, IN2, IN3 connected to respective input n-channel field effect transistor (NEFTs) N1, N2, N3, all of which are parallel to a common node 1. The first input IN1 is also connected to a an active pull-up p-channel field effect transistor (PFETs) P1 which is in series with the first NFET N1 and always maintained slightly on. A bipolar transistor T4 pulls down node 1 and a pair of bleeder NFETs N4, N5 pull down nodes 3 and 2, respectively. Output driver circuit 54 is comprised of bipolar transistors T1, T2, T3 arranged in a push-pull configuration.

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