Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-08-10
2002-03-12
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S758000, C257S763000, C438S132000
Reexamination Certificate
active
06355968
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabricating and more particularly, to an area efficient wiring scheme through a terminal via window.
2. Description of the Related Art
Current semiconductor circuits employ laser fuses to permit different circuit configurations to adjust functionality after a circuit is fabricated. A laser fuse includes a conducting wire (e.g., made of aluminum, tungsten, polysilicon, etc.) that can be blown or opened up (i.e., open circuit) by a laser beam applied externally from the chip or circuit. In memory circuits, such as, for example, dynamic random access memories (DRAMs), fuses are typically used to activate and configure redundant elements of the memory array to fix fabrication failures and increase the overall production yield. Depending on the number and granularity of the redundant elements, a standard DRAM may include more than 10,000 laser fuses. Due to this large number, the fuses are arranged in a regular fashion in fuse banks to simplify the fuse blow process.
Since the fuses must be accessible from the outside, passivation layers on top of the fuses are removed by an etch process. This process step creates an opening through the passivation layer called a TV (terminal via) window. Due to the height of the passivation and due to the characteristics of the etch process, the TV window typically does not have very steep and clear cut edges. Therefore, a relatively large spacing between different TV windows must be maintained, as shown in FIG.
1
.
Referring to
FIG. 1
, a cross section through two neighboring TV windows
10
and
12
is shown. A passivation layer
14
and an insulation layer
16
are opened up to form adjacent TV windows
10
and
12
and to expose laser fuses
16
(running perpendicular to the plane of the page). Laser fuses
16
are exposed to permit a laser beam to blow the appropriate fuses. Laser fuses
16
are formed on an insulating layer
18
, which is a safe distance from a substrate
20
.
Referring to
FIG. 2
, a top view of a typical layout with a TV window is shown. Wiring
22
is routed around a fuse bank
24
. Wiring
22
is formed below passivation layer and is indicated in the FIGS. for illustrative purposes. This configuration suffers from a significant area penalty as a minimum distance is required from laser fuses
26
of fuse bank
24
. Further, wiring
22
must not be exposed when opening up TV window
28
. To ensure that wiring
22
avoids being exposed an even larger area penalty is incurred.
Passivation layer
14
on top of the semiconductor circuit protects the underlying circuits and wires from corrosion thus contributing to the circuit's reliability. Therefore, it is typically not recommended to use wiring or circuits inside the TV window except the laser fuses
26
. As a consequence, all wiring must be routed around the TV windows
28
on the chip, which can cause a significant wiring overhead. This wiring overhead increases overall chip size, contributes to additional power consumption and slows down signal propagation due to the increased wiring parasitics (mainly resistance and capacitance).
Referring to
FIG. 3
, it is possible to split a TV window into two smaller TV windows
32
and
34
, if cross wiring
36
is required. However, as outlined before a required spacing
38
between separate TV windows
32
and
34
would cause a significant area overhead. This is essentially the same as having two TV windows (FIG.
1
).
Therefore, a need exists for an apparatus and wiring method for permitting wiring through a TV window, which reduces the area penalty associated with the prior art layouts.
SUMMARY OF THE INVENTION
A semiconductor device, in accordance with the present invention, includes a plurality of fuses disposed on a same level in a fuse bank. A plurality of conductive lines are routed through the fuse bank in between the fuses. A terminal via window is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.
In other embodiments, the plurality of conductive lines may pass below the level of the fuses. The plurality of conductive lines may include a top layer of conductive lines that pass on the same level of the fuses, the top layer of conductive lines including a corrosion resistant material. The corrosion resistant material may include tungsten. The fuse bank may include a wiring area for the plurality of conductive lines to pass, wherein the fuses adjacent to the wiring areas are disposed in accordance with a distance of n times p, where n is an integer and p is a fuse pitch. The plurality of conductive lines may be spaced apart from the fuses to prevent damage during a fuse blow. The plurality of conductive lines may include a top layer of conductive lines that pass on above the level of the fuses, the top layer of conductive lines including a corrosion resistant material.
In still other embodiments, the semiconductor device may further include an insulation layer disposed over the plurality of conductive lines within the terminal via window, and a plate formed on the insulation layer directly over the plurality of conductive lines to protect the conductive lines. The plurality of conductive lines may include at least one layer of conductive lines that are disposed above the level of the fuses, the at least one layer of conductive lines including a corrosion resistant material. The semiconductor device may include an insulation layer supporting the at least one layer of conductive lines within the terminal via window. The plurality of conductive lines may be included in a plurality of different levels.
A semiconductor device, in accordance with the present invention, includes a plurality of fuses disposed on a same level in a fuse bank, and a plurality of conductive lines routed through the fuse bank in between the fuses, the plurality of conductive lines including conductive lines on the same level of the fuses, below the level of the fuses and above the level of the fuses. A passivation layer is formed over the level of the fuse bank and the plurality of conductive lines, and a terminal via window is formed in the passivation layer over a portion of the plurality conductive lines and over the fuse bank, the terminal via window being formed to expose the fuses in the fuse bank.
In alternate embodiments, the plurality of conductive lines may include a first and a second layer of conductive lines. The first layer of conductive lines is disposed above the level of fuses, and the second layer of conductive lines is disposed on the same level of the fuses. The first and second layers of conductive lines include a corrosion resistant material. The corrosion resistant material may include tungsten. The fuse bank may include a wiring area for the plurality of conductive lines to pass, wherein the fuses adjacent to the wiring areas are disposed in accordance with a distance of n times p, where n is an integer and p is a fuse pitch. The plurality of conductive lines are preferably spaced apart from the fuses to prevent damage during a fuse blow. The semiconductor device may include an insulation layer disposed over the plurality of conductive lines within the terminal via window above the level of the fuses, and a plate formed on the insulation layer directly over the plurality of conductive lines to protect the conductive lines. The plurality of conductive lines are preferably included in a plurality of different levels.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5025300 (1991-06-01), Billig et al.
patent: 5235205 (1993-08-01), Bippitt, III
patent: 5550399 (1996-08-01), Okazaki
patent: 5589706 (1996-12-01), Mitwalsky et al.
patent: 5851903 (1998-12-01), Stamper
patent: 5949323 (1999-09-01), Huggins et al.
patent: 5986319
Brintzinger Christoph
Lehmann Gunther
Eckert II George C.
Infineon - Technologies AG
Lee Eddie
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