Wiring substrate having vias

Details Wiring substrate having vias Wiring substrate having vias

1998-05-01

2000-07-25

Lam, Cathy F.

Stock material or miscellaneous articles

Structurally defined web or sheet

Discontinuous or differential coating, impregnation or bond

428210, 428901, 174255, 174262, 174258, 439 65, 439 74, B32B 306

Patent

active

06093476&

ABSTRACT:
A wiring substrate is provided in which a common core member is used and the cost can be reduced. Diameters of the penetrating filled vias (18) are the same and not more than 300 .mu.m, and the penetrating filled vias (18) are formed on a core substrate (20) into a matrix-shape at regular intervals of not more than 2 mm. On the surface of the core substrate (20), a plane wiring pattern (17) is formed through an insulating layer (16). Each pad portion on the wiring pattern (17) is electrically connected with each corresponding via of the filled vias (18) by one to one through a connecting via (28) which penetrates the insulating layer (16), and some of the filled vias (18) are not connected with the wiring pattern (17).

REFERENCES:
patent: 3541222 (1970-11-01), Parks et al.
patent: 4954878 (1990-09-01), Fox et al.
patent: 5162240 (1992-11-01), Saitou et al.
patent: 5262226 (1993-11-01), Yoshida
patent: 5331514 (1994-07-01), Kuroda
patent: 5354955 (1994-10-01), Gregor et al.
patent: 5488542 (1996-01-01), Ito
patent: 5498467 (1996-03-01), Moela
patent: 5670250 (1997-09-01), Sanville, Jr. et al.
patent: 5851681 (1998-12-01), Matsuyama et al.

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