Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-02-04
2002-06-11
Cureo, Kamand (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C174S050510, C361S767000, C361S771000
Reexamination Certificate
active
06403895
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device package, in particular to a wiring substrate to be used for a package of a semiconductor device of a BGA (Ball Grid Array) type, and a semiconductor device employing such a wiring substrate.
BACKGROUND OF THE INVENTION
As shown in FIG.
8
(
a
) and FIG.
8
(
b
), in a conventional resin sealed type semiconductor device of a BGA type employing a bonding wire, a semiconductor chip
71
is provided, with its circuit portion facing above, on a substrate
73
on which a wiring pattern
72
is provided on the side where the semiconductor chip
71
is mounted. Also, a metal thin wire connection electrode pad
74
, which is an electrode terminal to be connected to the semiconductor chip
71
and which is provided at an end of each wiring of the wiring pattern
72
, is connected to an output terminal
71
a
of the semiconductor chip
71
by a metal wire
75
(thin wire). Thus, the wiring pattern
72
on the substrate
73
and the semiconductor chip
71
are electrically conducted, and thereafter sealing is made so that the semiconductor chip
71
, wiring pattern
72
, and wire
75
, etc., are coated with resin.
The resin sealed type semiconductor device includes a solder ball
76
(external terminal) which is provided on the other side of the resin sealed surface of the substrate
73
. The solder ball
76
constitutes a signal terminal for electrically connecting each wiring of the wiring pattern
72
to an external circuit via a perforation
73
a
(external terminal mounting perforation) provided through the substrate
73
. The resin sealed type semiconductor device is made into a final product by being cut into individual pieces of an external size (package size) of the resin sealed type semiconductor device per semiconductor chip
71
.
Some of such resin sealed type semiconductor devices adopt a wiring substrate in which wiring pattern
72
is made of a metal of a single layer. In this kind of resin sealed type semiconductor device, in the case where the number of external terminals, i.e., the number of signal terminals which need to be externally connected, is large and the semiconductor chip
71
is small as compared with the package size, the distance from the semiconductor chip
71
to the metal thin wire connection electrode pad
74
on the substrate
73
becomes long. As a result, there is a tendency that the length of the wire
75
for connecting the semiconductor chip
71
and the metal thin wire connection electrode pad
74
is increased. This tendency becomes more prominent when the external size of the resin sealed type semiconductor device is increased due to the increased number of external terminals, for example, by an increase in number of signal terminals, and/or when the size of the semiconductor chip
71
(semiconductor chip size) is reduced while the number of signal terminals remains unchanged.
Further, as the length of wire
75
is increased by the increased difference in size between the external size of the resin sealed type semiconductor device and the semiconductor chip
71
, the angle of wire
75
with respect to the semiconductor chip
71
(wire angle) becomes smaller, and the intervals between the wires
75
are reduced. Thus, such a resin sealed type semiconductor device poses the problem that the wires
75
are susceptible to coming into contact with each other in a resin sealing step after wire bonding.
As described, the number of external terminals comprises the biggest factor in determining the external size of the resin sealed type semiconductor device, and also causes the wire contact between wires
75
as induced by the difference in size between the external size of the resin sealed type semiconductor device and the semiconductor chip
71
. Other factors which determine the external size of the resin sealed type semiconductor device include, for example, the number of metal thin wire connection electrode pads.
When the metal thin wire connection electrode pads
74
are to be aligned in a single row as shown in FIG.
8
(
a
) in a large number, the metal thin wire connection electrode pads
74
cannot be confined within the external size of the resin sealed type semiconductor device, and it is required as a result to position the metal thin wire connection electrode pads
74
outside of the external size of the resin sealed type semiconductor device. In such a case, the external size itself of the resin sealed type semiconductor device needs to be made large and the problem of wire contact between wires
75
is induced.
Meanwhile, in order to align all the metal thin wire connection electrode pads
74
within a desired external size of the resin sealed type semiconductor device, the metal thin wire connection electrode pads
74
may be aligned in plural rows, e.g., in two rows, by shifting the positions of metal thin wire connection electrode pads
74
of adjacent wiring. However, with this method, the pitch of the metal thin wire connection electrode pads
74
becomes small, and causes the problem of wire contact between the wires
75
to occur in the vicinity of the metal thin wire connection electrode pads
74
, and also causes wire bonding tools to come into contact with each other, and thus this method still does not solve the problem of wire contact between wires
75
in the resin sealing step after connecting wires
75
. In particular, when the wire angle is small between the semiconductor chip
71
and the position of the metal thin wire connection electrode pads
74
on the substrate
73
, the distance between the wires
75
is further reduced, and the danger of contact between wires
75
and between wire bonding tools is increased.
Further, when the number of external terminals (signal terminals) is large and the pitch between external terminals is small, by various limitations such as, for example, wire length and wire angle, it may be necessary to provide the metal thin wire connection electrode pads
74
at a position from which wire bonding cannot be made directly from the semiconductor chip
71
. In such a case, the external terminals which are connected to such metal thin wire connection electrode pads
74
cannot be used as the signal terminals.
As described, the problem of wire contact, which often occurs when the semiconductor chip size is relatively smaller than the package size and when the number of metal thin wire connection electrode pads is large, is inflicted by wire length and wire angle.
A wiring pattern having a large number of metal thin wire connection electrode pads is disclosed, for example, in Japanese Unexamined Utility Model No. 84460/1989 (Jitsukaihei 1-84460) (published date: Jun. 5, 1989), in which plural kinds of semiconductor chips having different configurations are aligned and mounted on the same single substrate without any change in the wiring pattern. As shown in
FIG. 9
, the wiring pattern is provided such that on a substrate
84
mounting semiconductor chips
81
,
82
, and
83
(chip parts), plural lines L
1
to Ln are formed, and the lines L
1
to Ln are provided, at an end of each line, with a plurality of metal thin wire connection electrode pads P
1
to Pn and Q
1
to Qn (bonding pads) which are to be used for wire bonding with the output terminals
81
a
,
82
a
, and
83
a
of the semiconductor chips
81
,
82
, and
83
, respectively, by which the lines L
1
to Ln extend toward a heat generating body via the metal thin wire connection electrode pads Q
1
to Qn from the metal thin wire connection electrode pads P
1
to Pn as a starting point.
Thus, in the above wiring pattern, wire bonding is made in accordance with the shapes of the semiconductor chips
81
,
82
, and
83
so that, for example, with respect to the semiconductor chip
81
, the output terminals
81
a
of the semiconductor chip
81
and the exposed metal thin wire connection electrode pads P
1
and P
3
, P
2
m
−1, P
2
, P
4
, and P
2
m
on the first two rows are connected to each other by wire bonding, and with respect to the semiconductor chip
Cureo Kamand
Sharp Kabushiki Kaisha
Vu Quynh-Nhu H.
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