Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-03-26
2002-08-06
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S774000
Reexamination Certificate
active
06429519
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the use of a continuous highly conductive metal wiring structure in fabricating various semiconductor devices. More specifically, the present invention relates to a method of fabricating a wiring structure comprising a continuous single crystalline or polycrystalline conductive metal material extending through the structure which eliminates any interfaces between vias and lines contained within the structure. Damascene and non-damascene wiring structures are also provided by the present invention.
BACKGROUND OF THE INVENTION
A semiconductor chip contains an array of devices whose contacts are interconnected by patterns of conductive wires. In order to take full advantage of the device and the circuit density on a given chip, it is usually necessary to make interconnections among the various devices and circuit elements in the chip. However, due to the level of integration of devices and circuits on a chip, interconnections can no longer be made by means of a single level network of conductive lines. Often, it is necessary to form two or more such levels of conductive lines which are vertically spaced apart and separated by intermediate insulating layers.
Connections can be made between the different levels of conductive lines by means of vias which are etched through the insulating layer separating the levels. These vias are filled with a metal to form via studs. These multiple levels of conductor wiring interconnection patterns, with the individual levels connected by via studs, operate to distribute signals among the circuits on the chip.
In its simplest form, a via may be made by first masking an insulating layer with a photoresist and then selectively etching a portion of the insulating layer. The via is etched through an opening formed in the photoresist using well known photolithographic techniques to form an opening to the underlying conductive layer. Depending on the aspect ratio and the interconnection ground rules, isotropic or anisotropic etching processes may be used to form a hole in the dielectric.
After via etching, and photoresist removal, it is essential to deposit a conductive layer in the via. This deposited conductive layer forms an electrical interconnection between the conductive layers of the device. However, a liner or barrier layer is usually desirable between the insulative and conductive layers.
The presence of a liner layer on the sidewalls on the via is desirable because it enhances the structural integrity of the entire laminate. A good liner or barrier film effectively isolates the conductive metal from the dielectric as well as adhering firmly to the conductive metal and the dielectric. However, the best liner materials tend to be more resistive, as compared to conductive materials, so the presence of the liner at the bottom of the via increases the contact resistance of the structure. An increase in contact resistance is not desirable because it may lead to slower propagation of electrical signals through the wiring structure. For structural integrity, the liner should line the entire sidewall and will generally cover the bottom of the via as well.
Materials capable of forming a liner layer generally have a higher resistance than conductive materials. Liner materials have generally been selected to simultaneously minimize contact resistance, provide adequate adhesion between insulative and conductive materials, and provide a good diffusion barrier.
The contact resistance problem is compounded when copper, Cu, is used as the conductive metal. When Cu is used, the presence of a continuous dissimilar liner material with comparatively higher resistivity at the bottom of the via deters the fabrication of a single crystalline, or continuous, interface between the via conductor material and the wiring level below.
The formation of a single crystalline or polycrystalline interface in wiring structures is advantageous since it provides greater structural integrity for the interface between the via and the wiring level below. In the prior art, after via definition over a metal line, typically a continuous liner or barrier film is deposited on the sidewalls and bottom of the via. This is then followed with seed layer deposition over the liner. Finally, the via is filled with a metal using a suitable deposition method such as electroplating, CVD, electroless deposition or PVD techniques. In prior art wiring structures, the vias and lines are separated by a liner film; therefore an interface exists between the vias and the lines of the wiring structure.
A typical prior art wiring structure is shown in FIGS.
1
(
a
)-(
b
). Specifically, FIG.
1
(
a
) shows a typical via level
50
on a planarized metal level
52
. Via
50
consists of an opening in the dielectric that is landed on metal level
52
. The prior art via structure comprises a continuous liner layer
50
c,
a seed layer
50
b
and a conductive metal
50
a.
An interlevel dielectric
54
separates via level
50
from metal level
52
. After metal planarization, a plane of the liner layer
50
c
remains at the interface of the via and the trench.
In view of the drawbacks mentioned hereinabove, there remains a need of fabricating semiconductor devices which contain a continuous, single crystalline or polycrystalline conductive material, particularly Cu, between the various wiring levels of the semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a semiconductor device which contains no barrier material at the interfaces of the various wiring levels of the semiconductor device.
It is a further object of the present invention to provide a semiconductor device containing a continuous conductive metal microstructure running between lines and vias of the device which has an extremely low or relatively non-existent contact resistance compared with prior art devices.
It is another object of the present invention to provide a method of fabricating semiconductor devices in high yield having reduced maze or line resistance and having superior electromigration.
These as well as other objects will be achieved in the present invention by using an open-bottomed via liner structure in the semiconductor device. Specifically, the foregoing objects are met by the method of the present invention which comprises the steps of:
(a) providing an open-bottomed via liner structure comprising at least one via level located on top of at least one metal level, said via level having a liner material deposited only on the via's sidewalls;
(b) depositing a layer of conductive material to the open-bottomed via structure provided in step (a);
(c) forming a metal line layer on the conductive material;
(d) annealing said metal line layer under conditions effective to form a continuous, single crystalline or polycrystalline conductive material extending through the lines and vias of the structure; and
(e) planarizing the structure provided in step (d).
In one embodiment of the present invention, the structure provided in step (c) is encapsulated in a metal such as Ta, TaN, TiN, W, SiN and the like prior to annealing. Diamond-like carbon may also be used as an encapsulating material.
In another embodiment of the present invention, the annealing step is not performed. This is typically done when multilevel wiring structures are desirable.
The open-bottomed via liner structure employed in the present invention can be fabricated using conventional methods well known to those skilled in the art, but typically it is fabricated by the following steps:
(i) providing a planarized wiring structure having at least one metal level and at least one trench, wherein said trench contains a first liner material and is filled with a trench material;
(ii) optionally, depositing an interlevel dielectric layer on said metal level;
(iii) depositing an insulative material on said interlevel dielectric layer or said metal level;
(iv) patterning said insulative material to provide a via therein; and
(v) sputter depositing a secon
International Business Machines - Corporation
Picardat Kevin M.
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