Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1997-11-26
2001-05-22
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S759000, C257S760000, C257S775000
Reexamination Certificate
active
06236106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a multilayered wiring structure and a process for forming the same.
2. Description of Related Art
With an advanced microfabrication of the semiconductor device, a micro-multilayered wiring is indispensable to form the semiconductor device. An interlayer insulator film in the semiconductor device having the multilayered wiring structure is mainly formed of a silicon oxide film, which has a small dielectric constant and a stable quality, in order to reduce a parasite capacitance between an upper level wiring layer and a lower level wiring layer and between wiring conductors in the same level.
Because of the microfabrication of the semiconductor device, the width of the lower level wiring conductors and the spacing between adjacent wiring conductors are reduced, but in order to avoid an increase of a wiring resistance, it is necessary to ensure some degree of sectional area of the wiring conductor. As a result, an aspect ratio of wiring conductor (“height of wiring conductor” to “width of wiring conductor”) and an aspect ratio of inter-wiring spacing (“height of wiring conductor” to “spacing between adjacent wiring conductors”) become large. In addition, it is necessary to fill up a spacing between the lower level wiring conductors with the interlayer insulating film so as to planarize a surface of the interlayer insulating film.
Furthermore, when a large step exists on the surface of the interlayer insulating film, in a photolithographic process for forming the upper level wiring conductor, a fine resist pattern cannot be formed because of a shortage of the focus margin, or even if the fine resist pattern could be formed, disconnection of the upper level wiring conductor and/or an unetched remaining wiring material occur because of the large step. Therefore, it is required that the surface of the interlayer insulating film is planar.
In addition, the interlayer insulating film formed on the metal wiring conductor formed of aluminum is required to be formed at a temperature not higher than 450° C.
A spin-on-glass (SOG) process has been generally used as one typical method for forming the interlayer insulating film formed in a micro-multilayered structure formed of the metal wiring material formed of aluminum. However, this SOG has become difficult to uniformly planarize the whole of the semiconductor chip.
Now, the above mentioned situation will be described with reference to
FIGS. 1A
to
1
C, which are diagrammatic partial sectional views of a semiconductor device for illustrating a process of forming a lower level wiring conductor and an upper level wiring conductor, using the SOG film as a planarizing interlayer insulating film. In
FIGS. 1A
to
1
C, an inside of a semiconductor chip as well as an edge zone and a scribing line zone of the semiconductor chip are shown.
As shown in
FIG. 1A
, a field oxide film
102
is formed on a silicon substrate
101
, and a first level interlayer insulating film
103
is formed on the field oxide film
102
by a chemical vapor deposition (CVD) process. This first level interlayer insulating film
103
is formed of a silicon oxide film.
Then, lower level wiring conductors
104
,
104
A,
104
B and
104
C are formed on the first level interlayer insulating film
103
. The lower level wiring conductors
104
and
104
A are formed in the inside of the semiconductor chip, and the lower level wiring conductor
104
B is formed in the chip edge zone. These lower level wiring conductors are formed of for example metal aluminum or metal tungsten, and are used as a power supply line, a ground line or a signal line. This figure shows the power supply line or the ground line having a large line width of 20 &mgr;m. Similarly, the lower level wiring conductor
104
C formed of aluminum or tungsten, is formed in the scribing line zone of the semiconductor chip, and is connected to the silicon substrate
101
.
This lower level wiring conductor
104
C is indispensable to prevent generation of a channel leak current under the field oxide film, at a periphery of the semiconductor chip. Incidentally, in a DRAM (dynamic random access memory), this lower level wiring conductor
104
C is used as a wiring for a substrate potential generation circuit, or a discharge line for an electro-static discharge (ESD).
Thereafter, a second level interlayer insulating film
105
is formed to cover the lower level wiring conductors. This second level interlayer insulating film
105
is formed of a silicon oxide film having a film thickness of about 300 &mgr;m deposited by a plasma CVD process.
Furthermore, an SOG film
106
+
106
a
is formed on the second level interlayer insulating film
105
. This SOG film is formed by spin-coating an SOG coating solution on the second level interlayer insulating film
105
, and then, by heat-treating the spin-coated solution for a thermosetting. For example, this SOG film is formed of an organic silica film.
However, if the SOG film is formed as mentioned above, the film thickness of the SOG film is greatly different between the semiconductor chip inside and the semiconductor chip edge zone. For example, if it is so attempted that the SOG film
106
in the semiconductor chip inside has the film thickness of about 300 &mgr;m, the SOG fill
106
A in the semiconductor chip edge zone becomes 600 &mgr;m. The reason for this is that the SOG film is easy to remain on the lower level wiring conductors in the semiconductor chip edge zone because a surface tension. This phenomenon that the SOG film
106
A becomes thick in the semiconductor chip edge zone, becomes more remarkable if the line width of the lower level wiring conductor
104
B located in the semiconductor chip edge zone becomes large.
Then, a whole surface of the SOG file is etched back by a dry etching. With this etching-back, the SOG film on the lower level wiring conductors
104
and
104
A in the semiconductor chip inside are removed as shown in FIG.
1
B. However, the SOG film
106
remains between the lower level wiring conductors
104
and
104
A. Thus, the interlayer insulating film is planarized.
In the semiconductor chip edge zone, however, the SOG film
106
A remains on the lower level wiring conductors
104
B and
104
C. This is because the film thickness of the SOG film
106
A in the semiconductor chip edge zone is larger than that in the semiconductor chip inside, as mentioned above.
Thereafter, a third level interlayer insulating film
107
is formed by a plasma CVD process. This third level interlayer insulating film
107
is formed of a silicon oxide film having a film thickness of about 400 &mgr;m. In the semiconductor chip inside, the third level interlayer insulating film
107
is in direct contact with the second level interlayer insulating film
105
on the lower level wiring conductors
104
and
104
A. In the semiconductor chip edge zone, on the other hand, a stacked layer composed of the second level interlayer insulating film, the SOG film and third level interlayer insulating film is formed on the lower level wiring conductors
104
B and
104
C.
Thereafter, as shown in
FIG. 1C
, through holes
108
and
108
A are formed to penetrate through a stacked interlayer insulating film which is formed on the lower level wiring conductors
104
and
104
A and which is composed of the second interlayer insulating film
105
and the third interlayer insulating film
107
. Simultaneously, a through hole
108
B is formed to penetrate through the stacked layer which is formed on the lower level wiring conductor
104
B and which is composed of the second level interlayer insulating film, the SOG film and third level interlayer insulating film.
Furthermore, an upper level wiring conductor
109
is formed to connect through the contact hole
108
to the lower level wiring conductor
104
. Similarly, upper level wiring conductors
109
A and
109
B are formed to connect the lower level wiring conducto
Chaudhuri Olik
Eaton Kurt
Laff, Whitesel & Saret, Ltd.
NEC Corporation
Whitesel J. Warren
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