Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
1999-08-16
2002-09-03
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S622000, C438S158000
Reexamination Certificate
active
06444484
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for connecting conductive lines formed on separate layers with an intervening insulation layer. More particularly, the present invention relates to a method of manufacturing a semiconductor device having a plurality of thin film transistors, such as memories and liquid crystal display devices, and a wiring structure on different layers.
2. Description of the Related Art
The number of thin film transistors (TFTs) integrated in a unit area is a very important parameter in manufacturing a high density and micro-sized semiconductor device or a high resolution liquid crystal display (LCD) device. In order to design a high-capacity memory device or an LCD device with higher resolution than XGA (Extended Video Graphic Array), the number of TFTs per unit area must be increased. Therefore, bus lines connected to the TFTs are squeezed into ever narrower areas. Therefore, the area used to connect the gate line of the TFT to another line must decrease as well.
A conventional method for connecting bus lines formed on separate layers, and a wiring structure formed by the same method, is as follows.
FIG. 1
a
shows the cross-sectional view of the bus lines formed in separate layers using a conventional method.
FIG. 1
b
shows a plan view of the wiring structure formed using the conventional method.
FIGS. 2
a
-
2
d
show the manufacturing process of the same.
A metal layer, such as aluminum or an aluminum alloy, is deposited on a substrate
11
. The metal layer is patterned to form a low resistance gate line
15
a
. The surface of the low resistance gate line
15
a
can generate a hillock. A metal layer including chromium or molybdenum is deposited on the substrate
11
. The metal layer is patterned to form a second-metal gate line
15
covering the low resistance gate line
15
a
, as shown in
FIG. 2
a
. The second-metal gate line
15
prevents formation of a hillock on the low resistance gate line
15
a.
An insulation material, such as silicon oxide or silicon nitride, is deposited on the substrate
11
having the second-metal gate line
15
to form a gate insulation layer
19
. A metal layer, such as chromium or a chromium alloy, is deposited on the gate insulation layer
19
, as shown in
FIG. 2
b
. The metal layer is patterned to form a source line
35
. The source line
35
is connected to a source electrode of a switching element, such as a TFT.
An insulation material, such as silicon nitride or silicon oxide, is deposited on the substrate
11
having the source line
35
to form a protection layer
39
. As shown in
FIG. 2
b
, the low resistance gate line
15
a
and the second-metal gate line
15
, and the source line
35
are located on separate layers, with the gate insulation layer
19
positioned between them. The second-metal gate line
15
and the source line
35
should not normally be connected to each other, because they are used for different purposes. However, they need to be connected to each other during some processing steps, in order to protect the substrate from static electricity damage. For example, if a repair line for source line
35
is formed on the same layer of the same material as the second-metal gate line
15
, then the source line
35
should be connected to the repair line. In order to connect the source line
35
to the second-metal gate line
15
(or to the repair line on the same layer as the second-metal gate line
15
), a gate contact hole
41
and a source contact hole
51
are first formed, as shown in
FIG. 2
c
. The gate contact hole
41
exposes a portion of the second-metal gate line
15
by etching the protection layer
39
and the gate insulation layer
19
. The source contact hole
51
exposes a portion of the source line
35
by etching the protection layer
39
covering the source line
35
.
A layer of conductive material, such as indium tin oxide (ITO), is deposited on the protection layer
39
. The ITO layer is patterned to form a connecting pad
53
. The connecting pad
53
connects the second-metal gate line
15
and the source line
35
through the gate contact hole
41
and the source contact hole
51
, as shown in
FIG. 2
d.
In the conventional method for connecting bus lines formed on separate layers, the lines are connected by a third conductive material through the contact holes formed in same plane. Therefore, space for the contact holes must be reserved. Therefore, there is a limitation to manufacturing a higher density semiconductor device using the conventional method. When manufacturing a high density semiconductor device, all building components of the device become smaller and smaller. Thus, the gate lines and the source lines become narrower and narrower. Furthermore, as the number of connecting parts increases, the area needed for connecting hinders higher integration.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a wiring structure of a thin film transistor array and method of manufacturing the same that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to reduce the amount of area needed for connection lines in manufacturing the electrical circuit board, including multiple layers of bus lines.
Another object of the present invention is to simplify the process for connecting metal lines formed on separate layers.
Additional features and advantages of the present invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and process particularly pointed out in the written description as well as in the appended claims.
To achieve these and other advantages and according to the purpose of the present invention, as embodied and broadly described, in a first aspect of the present invention there is provided a method for fabricating a semiconductor device on a substrate including the steps of forming a first conductive layer on the substrate, forming an insulation layer on the first conductive layer, forming a second conductive layer having a first portion overlapping the first conductive layer, removing a portion of the first portion of the second conductive layer that overlaps the first conductive layer to form a top contact hole exposing a portion of the insulation layer, removing the exposed portion of the insulation layer through the top contact hole to form an enlarged contact hole, and forming a conductive pad in contact with the first conductive layer and the second conductive layer through the enlarged contact hole.
In a second aspect of the present invention there is provided a method for fabricating a semiconductor device on a substrate including the steps of forming a first conductive layer on the substrate, forming a first insulation on layer on the first conductive layer, forming a second conductive layer having a first portion overlapping the first conductive layer, forming a second insulation layer on the second conductive layer, removing selected portions of the second insulation layer, the second conductive layer and the first insulation layer to form contact hole at a position corresponding to the first portion of the second conductive layer, and forming a conductive pad in contact with the first conductive layer and the second conductive layer through the contact hole.
In a third aspect of the present invention there is provided a semiconductor device, including a substrate, a first conductive layer on the substrate, an insulation layer covering the first conductive layer and having a first contact hole exposing a portion of the first conductive layer, a second conductive layer having an overlapping portion overlapping the first conductive layer, the overlapping portion having a second contact hole exposing the portion of the first conductive layer that is exposed through the first contact
LG Electronics Inc.
Morgan & Lewis & Bockius, LLP
Wilczewski Mary
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