Wiring structure of source line used in semicustom integrated ci

Details Wiring structure of source line used in semicustom integrated ci Wiring structure of source line used in semicustom integrated ci

1993-03-25

1996-07-23

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257500, 257203, H01L 2182, H01L 2704

Patent

active

055392237

ABSTRACT:
A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.

REFERENCES:
patent: 4563601 (1986-01-01), Asano et al.
patent: 5067003 (1991-11-01), Okamura
patent: 5223744 (1993-06-01), Ohbayashi et al.
Vu et al., "A Gallium Arsenide SDFl Gate Array with On-Chip Ram, " IEEE Journal of Solid-State Circuits, vol. SC-19, No. 1, pp. 10-22, (1984).
"A 209K-Transistor ECL Gate Array with RAM", Satoh et. al., IEE Journal of Solid-State Circuit, 24(5):1275-1279 (1989).

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