Wiring structure of a semiconductor integrated circuit and a...

Details Wiring structure of a semiconductor integrated circuit and a... Wiring structure of a semiconductor integrated circuit and a...

1998-07-10

2002-08-20

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S262000, C257S365000, C438S622000, C438S687000

Reexamination Certificate

active

06437441

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a wiring structure for use in a semiconductor integrated circuit in which wiring capacitance is effectively reduced and operational speed is improved and a method of forming the wiring structure. This invention also relates to a semiconductor integrated circuit in which the advantages of a low resistance wiring are fully utilized while production and development costs are minimized.
2. Description of Related Art
Historically, in a semiconductor integrated circuit, as the design parameters or minimum feature sizes have been reduced by improved fabrication technologies, both the number of elements which can be integrated in a semiconductor chip and the operational speed have been improved. The main reason for improved operational speed is that the switching speed of transistors has been improved as the dimensions i.e., the gate length in the case of a MOS transistor, have been reduced.
However, if the design rule, usually expressed by the minimum gate length of a transistor, becomes less than about 0.5 &mgr;m, the size reduction of this feature does not always ensure improved operational speed. The main reason for this is that signal propagation time over long distance wiring between circuit blocks within an integrated circuit chip tends to increase as the feature size decreases.
In other words, the resistance per unit length increases as the feature size decreases because of the decrease in the cross-sectional area of the wiring. In addition, the capacitance per unit length also increases as the feature size decreases because the space between wires is reduced while the height of the wires is kept almost constant. Also, the dimensions of the chip tends to increase as the design rule decreases because the number of transistors integrated onto the chip increases more rapidly compared to the decrease in the size of the transistor. Therefore, the average wiring length between the circuit blocks tends to increase as the design rule decreases. Accordingly, as feature size decreases the resistance of the wire and the capacitance between the wires increases, and the signal propagation time over the wiring between circuit blocks, which is roughly determined by the product of the resistance and the capacitance, tends to increase. Therefore, in order to improve the operational speed of a semiconductor integrated circuit, in particular, in a semiconductor integrated circuit with a design size of 0.5 &mgr;m or less, the resistance of the wire and the capacitance between the wires needs to be reduced.
Conventionally, wiring mainly formed of aluminum or aluminum alloys (hereafter “aluminum-based wiring”) was used for metal wiring in semiconductor integrated circuits. Silicon oxide formed by chemical vapor deposition (CVD) is generally used as a dielectric layer for the insulation between wires in the same wiring layer and for the insulation between upper and lower wiring layers. Pure silicon oxide has a dielectric constant of 3.9, while silicon oxide formed by CVD generally has a dielectric constant of approximately 4.0-4.4. The dielectric layer for the insulation between wiring layers is referred to as the “interlayer dielectric layer”, while the dielectric layer for the insulation between wires in the same wiring layer is referred to as the “intra-layer dielectric layer”, when it is necessary to distinguish between these two dielectric layers. However, these dielectric layers are usually formed integrally, and are usually collectively referred to as the “interlayer dielectric layer”.
In order to reduce wiring capacitance, use of insulating materials having lower dielectric constants than that of silicon oxide has been considered. At the same time, in order to reduce the wiring resistance, use of wiring mainly formed of metals having resistivities lower than that of aluminum, such as silver, copper and gold has been considered. Among them, wiring mainly formed of copper or copper alloy (hereafter “copper-based wiring”) has been widely investigated.
Aluminum-based wiring is usually formed by depositing a metal film on the entire surface of an insulating layer followed by selectively etching unnecessary portions of the metal film (hereafter “etching method”). In contrast, formation of copper-based wiring by forming grooves in a dielectric layer, followed by forming a copper or copper alloy film within the grooves, (hereafter “damascene method”) has been examined. (M. T. Bohr, IEEE International Electrons Devices Meeting Digest of Technical Papers (1995) p. 241, J. Paraszczak et al., IEEE International Electrons Devices Meeting Digest of Technical Papers (1993) p. 261).
The materials described below have been examined because they have lower dielectric constants than silicon oxide.
1) Fluorinated Silicon Oxide
A technology has been developed in which a fluorinated silicon oxide film is formed by CVD using an atmosphere in which a fluorine compound gas is added to a conventional silicon oxide CVD atmosphere. The dielectric constant of the fluorinated silicon oxide film is about 3.0-3.7, and it can be decreased by increasing the amount of added fluorine. In practice, however, the dielectric constant can be lowered only to about 3.3, since the film becomes hygroscopic if the amount of added fluorine is increased too much (H. Miyajima et al., Proceedings of Symposium on Dry Process, (1994), p. 133, R. Katsumata et al., Proceedings of Symposium on Dry Process, (1995), p. 269).
2) Siloxane SOG
For lower dielectric constant materials, various siloxane SOG (spin-on-glass) materials have been examined. In this technology, a coating solution which includes siloxane oligomers is coated on a substrate and cured to form a SOG film. The siloxane oligomer includes Si—O and Si—R (R═H, CH
3
, C
6
H
5
etc.) bonds. The dielectric constant of the SOG film is about 2.8-3.3. For example, hydrogen silsesquioxane SOG (B. T. Ahlbum et al., Proceedings of the 1
st
International Dielectrics for ULSI Multi-level Interconnection Conference (1995) p. 36) and methyl-siloxane SOG (K. Numata et al., Materials Research Society Symposium Proceedings, Vol. 381 (1995) p. 255) have been widely examined.
3) Organic Material
Organic materials, such as: polyimides, including BPDA-PDA, fluorinated polyimide, polyimide siloxane, fluorinated resin/siloxane copolymer, benzocyclobutene, parylene-F, poly(fluorinated naphthalane), amorphous Teflon™, fluorinated poly(arylethers), cyclo-perfluorocarbon polymer, and fluorinated amorphous carbon have been examined as low dielectric constant materials. Many of these materials are formed by a coating method, such as spin coating. However, some of these materials, e.g., fluorinated amorphous carbon, are formed by CVD. See, for example, C. H. Ting et al., Materials Research Society Proceedings, Val. 381 (1995) p. 3 C.-1, Lang et al., Materials Research Society Proceedings, Val. 381 (1995) p. 45, M. Mills et al., 1
st
International Dielectrics for ULSI Multilevel Interconnection Conference (1995) p. 269, S.-P. Jeng et al., Materials Research Society Symposium proceedings, Val. 381 (1995) p. 197, B. C. Auman, 1
st
International Dielectrics for ULSI Multilevel Interconnection Conference (1995) p. 297, N. H. Hendricks et al., 1
st
International Dielectrics for ULSI Multilevel Interconnection Conference (1995) p. 283, K. Endo et al., Japanese Journal of Applied Physics, Vol. 35 (1996) p. 1348.
4) Porous Material
It is possible to decrease the dielectric constant by decreasing the density of the dielectric film. As an extreme example, a dielectric constant of 1 can be obtained by providing a vacuum or an inert gas between wires. One method of decreasing the density is to form pores in the dielectric film. For example, an organic porous material (K. R. Carter et al., Materials Research Society Symposium Proceedings. Vol 1. 381 (1995) p. 79) or an inorganic porous material, such as a gel type silica (U.S. Pat. No. 5,488,015), have been investigated. The later material is often referred to as Xerogel™ or nano-porous silica

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