Patent
1990-09-20
1991-07-16
Prenty, Mark
357 45, 357 68, 357 71, H01L 2702, H01L 2710, H01L 2348, H01L 2946
Patent
active
050328891
ABSTRACT:
A wafer-scale integrated circuit includes a plurality of functional blocks, a plurality of respectively corresponding connection terminals being provided in each of the functional blocks. Respectively corresponding pluralities of layered wirings and bonding wires interconnect predetermined, respective ones of said corresponding connection terminals in parallel for supplying power source and other voltages in common to the plurality of functional blocks. The parallel interconnections by the layered wirings and bonding wires, due to different, respective failure modes, affording increased reliability.
REFERENCES:
patent: 4580259 (1986-04-01), Harada et al.
Iryu Toshihiko
Kikuchi Takeo
Murao Toshiaki
Nomura Hidenori
Sugamoto Hiroyuki
Fujitsu Limited
Prenty Mark
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