Wiring structure for an integrated circuit

Details Wiring structure for an integrated circuit Wiring structure for an integrated circuit

2002-10-02

2003-12-16

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S211000, C257S207000, C257S208000, C257S209000, C257S758000, C257S773000, C257S776000

Reexamination Certificate

active

06664641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring structure of an integrated circuit which takes into account a resistance and a capacitance associated with an electric wire in the wiring structure.
2. Description of the Background Art
Wiring of an integrated circuit is broadly divided into two categories: (1) signal wiring for transmitting a signal or a clock; and (2) ground/power-supply wiring for providing a power supply potential or a ground potential.
For (1) the signal wiring, it is important to reduce a delay time in signal transmission, which requires reduction of an RC delay time obtained based on a product of a wire resistance R and a wire capacitance C.
On the other hand, for (2) the ground/power-supply wiring, it is important to reduce an IR drop of a (power-supply/ground) voltage, and thus it is preferable to reduce a wire resistance R, as generally known.
In most cases, signal wiring is accomplished using a wire width W and a wiring space S which fit in a minimum wiring pitch defined for each wiring layer, in order to increase a wiring density.
FIG. 16
is a plan view of a conventional wiring structure of an integrated circuit. As shown therein, a plurality of signal wires
21
and a plurality of ground/power wires
22
, each of which has a wire width W
5
, are arranged, and a wiring space S
5
is provided between every two adjacent wires. Further, via holes
3
are provided at respective predetermined portions in the wires
21
and
22
. The signal wires
21
and the ground/power wires
22
are electrically connected with another wiring layer (not shown) located thereunder, through the via holes
3
.
A sum of a minimum wire width W and a minimum wiring space S corresponds to, and is referred to as, a minimum wiring pitch P of a wiring layer having the foregoing wiring structure. According to the conventional wiring structure, a wire width W and a wiring space S are determined to be substantially identical to each other, so that the wire width W
5
is determined to be approximately 50% of a wiring pitch. To achieve the minimum wiring pitch P, the wire width W
5
and the wiring space S
5
are determined as W
5
=S
5
=P/2, which is illustrated in FIG.
16
.
FIG. 17
is a sectional view schematically showing a section of the structure of
FIG. 16
taken along a line C—C of FIG.
16
. As shown therein, each of the signal wires
21
and the ground/power wires
22
has a wire thickness T
5
as a wire thickness T. The wire thickness T
5
is determined so as to keep an aspect ratio (T
5
/W
5
) which is a ratio of the wire thickness T
5
to the wire width W
5
of the signal wires
21
and the ground/power wires
22
smaller, than 2, for the reasons discussed below.
A wire resistance R of an electric wire having a wire width W is given by {R=&rgr;·L/(W·T)} wherein &rgr; represents a resistivity of a wire material and L represents a wire length. On the other hand, an inter-wire capacitance (coupling capacitance) provided between two electric wires which are arranged adjacent to each other with a wiring space S therebetween is approximated by {Cc=∈·T·L} wherein ∈ represents a dielectric constant of an interlayer insulating film.
For the purpose of reducing a resistance, which is required in ground/power-supply wiring, increase of a wire width W is effective as expected from the above-noted equation for the wire resistance R. However, increase of a wire width W has a non-negligible disadvantage of inviting decrease of wiring density.
Then, as an alternative to increase of a wire width W, increase of a wire thickness T is effective in reducing a resistance of an electric wire. Japanese Patent Application Laid-Open No. 11-274154 has paid a particular attention to that procedure, and discloses a wiring method in which a wire thickness T of each signal wire and a wire thickness T of each ground/power wire are made different from each other.
FIGS. 18
to
20
are sectional views for showing the wiring method disclosed in the above-identified reference. More particularly, those figures illustrate a method of forming second metal wires to be electrically connected with first metal wires
300
disposed within a silicon dioxide film (SiO
2
film)
301
on a silicon substrate
200
in which a device such as a MOS transistor is to be formed. The first metal wires
300
are electrically connected to a source/drain region, a gate electrode and the like of the MOS transistor.
In accordance with the method disclosed in the above-identified reference, firstly, a silicon nitride film
302
, a silicon dioxide film
303
, a silicon nitride film
304
, a silicon dioxide film
305
and a silicon nitride film
306
are sequentially deposited in this order on the silicon dioxide film
301
, to form a stack of layers. The silicon nitride films
302
,
304
and
306
differ from the silicon dioxide films
301
,
303
and
305
in etch selectivity in predetermined etching.
Thereafter, a resist pattern
307
is formed on the silicon nitride film
306
. The resist pattern
307
includes an opening
311
in a first region A
1
(region for formation of signal wires) which is to contain electric wires each having a relatively small thickness. The opening
311
corresponds to a width of a via hole to be formed in each signal wire. The resist pattern
307
further includes an opening
312
in a second region A
2
(region for formation of ground/power wires) which is to contain electric wires each having a relatively large thickness. The opening
312
corresponds to a wire width of each ground/power wire. Then, the films
303
to
306
in the stack of layers are etched using the resist pattern
307
as a mask, and the resist pattern
307
is removed.
Next, a resist pattern
308
is formed as shown in FIG.
19
. The resist pattern
308
includes an opening
313
which corresponds to a width of each signal wire in the first region A
1
. The resist pattern
308
further includes an opening
314
which corresponds to a via hole to be formed in each ground/power wire in the second region A
2
. Then, the films
301
and
302
in the stack of layers are etched using the resist pattern
308
as a mask, and the resist pattern
308
is removed.
Subsequently, Ti/TiN is deposited. Thereafter, aluminum is sputtered, so that the aluminum is buried in the via holes and wiring patterns which are opened in the first region A
1
and the second region A
2
. Then, metals (Ti/TiN and aluminum) except portions thereof buried in trenches for wiring are removed using CMP. As a result, metal wires
309
to be electrically connected to the first metal wires
300
through via holes Via can be formed in the first region A
1
and the second region A
2
.
At that time, each of the metal wires
309
in the first region A
1
where the metal wires
309
are to function as signal wires and thus increase of an inter-wire capacitance is a matter of the most serious concern has a reduced thickness as compared with that of the metal wires
309
in the second region A
2
where the metal wires
309
are to function as ground/power wires and thus increase of resistance is a matter of the most serious concern. This allows for improvement in performance of an LSI.
However, to provide different wire thicknesses T for the signal wires
21
and the ground/power wires
22
would complicate a manufacturing process. For this and other reasons, significant problems would be produced, and thus the method described above is not suitable for practical use. In other words, it is desirable that the signal wires
21
and the ground/power wires
22
have the same wire thickness T, which eliminates a need of employing a special manufacturing method shown in
FIGS. 18 and 20
, thereby to allow for reduction in manufacturing cost.
To commonize the wire thicknesses T of the signal wires
21
and the wire thickness T of the ground/power wires
22
, in turn, would involve increase of the wire thickness T of the signal wires
21
which are usually formed using the minimu

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